Asynchronous FIFO Ping-Pong Control for Variable-Length Video Data
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Solution Overview
Problem
Existing methods for interface bridging in electronic devices face challenges in effectively controlling dual-FIFO ping-pong buffer read/write operations, particularly when dealing with data streams of variable packet lengths, leading to read/write conflicts and difficulties in asynchronous buffer processing.
Innovation Solution
An asynchronous FIFO read/write control method that involves parsing data packet length, determining an almost empty threshold for dual-FIFO queues, and performing ping-pong writes and reads based on this threshold and the minimum time interval of the back-end interface, with optional inter-lane sequence reordering and dynamic threshold adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous clock-based dual-FIFO ping-pong buffer read/write is used for interface bridging, then the processor can handle variable packet length data, but read/write conflicts easily occur
Solution Approach 1:
The patent introduces an intermediary control mechanism consisting of read/write control registers and status flags that mediate between the write interface and read interface. These intermediaries coordinate the ping-pong buffer operations by managing the almost empty thresholds and read enable signals, preventing direct read/write conflicts while maintaining asynchronous operation and variable packet length support.
Solution Approach 2:
The patent implements feedback mechanisms through status flags (such as almost empty flags) that provide information about the buffer state back to the read control logic. This feedback enables the system to dynamically adjust read operations based on current buffer conditions, preventing read/write conflicts while maintaining efficient data flow for variable packet lengths.
2Reliability
If dedicated bridge is used for interface bridging, then the function is specialized, but the expansibility is poor and costs are relatively high
Solution Approach 1:
The patent implements a universal processor-based solution that can handle multiple interface bridging scenarios through software configuration rather than hardware specialization. The dual-FIFO ping-pong buffer mechanism is designed to be adaptable to different packet lengths and data rates by modifying control parameters, providing both reliable interface bridging and excellent expansibility without requiring dedicated hardware bridges.
Solution Approach 2:
The patent employs dynamic control parameters including adjustable almost empty thresholds and configurable buffer depths that can be adapted to different application requirements. This dynamic configuration capability allows the same hardware structure to serve multiple functions and scale to different needs, eliminating the need for specialized dedicated bridges for each scenario.
3Adaptability or versatility
If processor-based interface bridging is used, then expansibility is improved, but read/write conflict occurs in dual-FIFO ping-pong buffer
Solution Approach 1:
The patent introduces intermediary control mechanisms including read control registers and write control registers that act as mediators between the processor and the dual-FIFO ping-pong buffer. These intermediaries manage the timing and coordination of read/write operations, preventing conflicts while maintaining the expansibility benefits of the processor-based approach.
Solution Approach 2:
The patent implements feedback control through status flags that communicate buffer state information to the processor. This feedback enables the processor to make informed decisions about read/write timing, preventing conflicts while maintaining system expansibility. The almost empty flag and other status indicators provide real-time information for coordinated operation.
Data Source
AI summary
Disclosed are an asynchronous FIFO read/write control method and system, and an electronic device, belonging to the technical field of data read/write technology. The asynchronous FIFO read/write control method comprises: parsing data received by a front-end interface to obtain a data packet length and valid video data; determining an almost empty threshold of a first FIFO queue and a second FIFO queue according to the data packet length, and writing the valid video data into the first FIFO queue and the second FIFO queue in a ping-pong manner; determining a minimum time interval of FIFO readings according to a sending time sequence of a back-end interface, and reading data from the first FIFO queue and the second FIFO queue in the ping-pong manner according to the almost empty threshold and the minimum time interval, so as to output the read data through the back-end interface.