Asynchronous FSM Circuit Synthesis for Non-Persistent Inputs
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Solution Overview
Problem
Existing asynchronous circuits face challenges in designing efficient and reliable asynchronous finite state machines due to issues with non-persistent inputs and propagation delays, leading to undesired circuit operations and hazards.
Innovation Solution
A computer-implemented method for generating asynchronous circuit designs, including the creation of state and transition data packages, which are used to generate circuit block and wire data packages, enabling the synthesis of quasi delay-insensitive asynchronous circuits with sanitization layers to handle non-persistent inputs and ensure well-behaved operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If asynchronous circuits use non-persistent inputs directly, then the circuit can respond quickly to changes, but the circuit operation becomes unreliable due to propagation delays and hazards
Solution Approach 1:
The patent applies preliminary action by converting non-persistent inputs to persistent signals before they enter the asynchronous finite state machine. This preprocessing step ensures that input signals maintain their logical state long enough for reliable processing, preventing hazards while preserving the speed advantages of asynchronous operation. The conversion occurs in advance, allowing the main circuit to operate without waiting for signal stabilization.
Solution Approach 2:
The patent introduces an intermediary conversion mechanism that transforms non-persistent inputs into persistent signals. This intermediary layer acts as a buffer between the fast-changing external inputs and the asynchronous finite state machine, mediating the conflict between speed and reliability. The conversion process ensures signals are stable enough for reliable processing without significantly delaying the overall response time.
2Adaptability or versatility
If asynchronous circuits implement complex state transition logic, then the circuit functionality increases, but the circuit complexity and design difficulty increase
Solution Approach 1:
The patent applies segmentation by dividing the asynchronous finite state machine into distinct functional blocks: input conversion logic, state transition logic, and output logic. Each block handles a specific aspect of the state machine operation, making the overall complex circuit more manageable and easier to design. The segmentation allows independent optimization of each block while maintaining overall functionality.
Solution Approach 2:
The patent utilizes parameter changes by representing circuit states and transitions through structured data formats with defined parameters. By changing the representation parameters from traditional gate-level design to data-package-based state descriptions, the patent simplifies the design process while maintaining complex functionality. The parameter-based approach allows systematic generation of circuit implementations from high-level specifications.
3Productivity
If asynchronous circuits operate without clock synchronization, then the circuit efficiency increases, but the design precision and reliability decrease
Solution Approach 1:
The patent applies self-service by implementing automatic conversion of non-persistent inputs to persistent signals within the circuit architecture. This self-service mechanism eliminates the need for external clock synchronization while maintaining design precision. The circuit automatically handles signal stabilization, allowing asynchronous operation to proceed efficiently without compromising reliability through manual intervention or complex synchronization protocols.
Data Source
AI summary
A computer-implemented method for generating a circuit design for an asynchronous circuit having an asynchronous finite state machine circuit is provided. The method includes receiving a first data file having state transition data that describes an asynchronous finite state machine. The method further includes generating, from the state transition data, a plurality of state data packages and one or more transition data packages. Each state data package is representative of a state of the asynchronous finite state machine. Each transition data package is representative of a transition between two states of the asynchronous finite state machine. The method further includes generating a second data file having circuit design data for the asynchronous circuit, thereby generating the circuit design for the asynchronous circuit.