Asynchronous GPS Baseband Processor Power Reduction
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Solution Overview
Problem
Existing GPS receiver chips face high power consumption issues, leading to overheating and limited continuous operation in mobile devices, which hinders advancements in location-aware applications and micro robotics navigation.
Innovation Solution
An asynchronous GPS baseband processor architecture utilizing Quasi-Delay-Insensitive (QDI) and bundled-data techniques, allowing all subsystems to operate at their natural frequency without clocking, with on-the-fly signal processing and shared tracking loops to minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a powerful DSP is used to perform all baseband processing in software, then reconfigurability and ease of development are improved, but power consumption increases significantly
Solution Approach 1:
The baseband processor is segmented into dedicated hardware correlation engines for fast correlation operations and a microprocessor for higher-level signal processing tasks. This segmentation allows each component to operate at optimal efficiency, with the hardware engine handling power-intensive correlation computations while the microprocessor manages reconfigurable processing functions.
Solution Approach 2:
Software-based baseband processing is partially replaced with dedicated hardware correlation engines that perform fast correlation operations through hardware circuitry rather than software execution. This substitution dramatically reduces the processing burden on the microprocessor and enables lower overall power consumption while maintaining reconfigurability through hardware/software cooperation.
2Speed
If a hardware correlation engine is used to handle fast correlation operations, then processing speed is improved, but power consumption of the baseband processor increases
Solution Approach 1:
The system dynamically allocates tasks between the hardware correlation engine and the microprocessor based on processing requirements. The hardware engine handles time-critical correlation operations at high speed, while the microprocessor manages slower but more complex signal processing tasks, creating a dynamic workload distribution that optimizes both speed and power consumption.
Solution Approach 2:
The system changes operational parameters by switching between hardware-accelerated correlation mode and software-based processing mode depending on the specific processing requirements. This parameter change allows the system to achieve high processing speeds when needed while reducing power consumption during less demanding operations.
3Stability of the object's composition
If conventional clocked architectures are used, then system stability is improved, but power consumption increases due to continuous clocking of all subsystems
Solution Approach 1:
Instead of continuous clocking, the system uses periodic handshaking and event-driven operation where subsystems are activated only when needed. The asynchronous architecture with handshaking mechanisms provides stability through controlled signal propagation while eliminating continuous clocking power consumption.
Solution Approach 2:
The system changes the timing parameter from continuous synchronous clocking to asynchronous event-driven operation. Each subsystem operates independently at its own pace, triggered by events from previous stages, which maintains system stability through proper sequencing while dramatically reducing power consumption by eliminating continuous clock signals.
Data Source
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AI summary
Asynchronous Global Positioning System (GPS) baseband processor architectures with a focus on minimizing power consumption. All subsystems run at their natural frequency without clocking and all signal processing is done on-the-fly.