Asynchronous IC Pipeline Timing for Clockless Chip Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuits face challenges in proximity communication between adjacent chips or semiconductor die, as they often rely on shared clock signals, leading to increased power consumption and cost, and without a common clock, it is difficult for receiving chips to synchronize data capture from capacitive coupling networks.
Innovation Solution
An integrated circuit with multiple stages of asynchronous circuits and connectors for proximity communication, where a first state wire provides advanced notice to a corresponding state wire on another integrated circuit, allowing for approximately synchronous operation without a common clock, using GasP pipelines to extend timing signals and facilitate simultaneous data communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common clock signal is shared between integrated circuits for proximity communication, then synchronous data capture and communication timing is achieved, but power consumption and chip area increase significantly
Solution Approach 1:
The patent extracts the clock signal generation function from each integrated circuit, eliminating the need for shared clock distribution. Each circuit operates independently with its own clock, removing the power-consuming clock distribution network while maintaining synchronization through handshake protocols between circuits.
Solution Approach 2:
The patent implements feedback mechanisms where circuits exchange timing information and acknowledgment signals to coordinate data transfer. This feedback loop allows asynchronous circuits to synchronize their operations without requiring a shared clock signal, resolving the contradiction between synchronization reliability and power consumption.
2Reliability
If a common clock signal is shared between integrated circuits, then synchronous operation is achieved, but chip area and cost increase
Solution Approach 1:
The patent removes the clock distribution network from the system architecture, extracting the timing synchronization function from the physical clock signal infrastructure. This eliminates the area-consuming clock trees and distribution circuits while maintaining timing coordination through software or protocol-based synchronization.
Solution Approach 2:
The patent introduces intermediary handshake signals and timing protocols that mediate between independent clock domains. These intermediary mechanisms coordinate data transfer between circuits without requiring direct clock signal sharing, reducing the area needed for clock distribution infrastructure.
3Use of energy by moving object
If asynchronous circuits are used without a common clock, then power consumption and chip area are reduced, but it becomes difficult for receiving chips to know when to capture data
Solution Approach 1:
The patent implements preliminary action by having transmitting circuits send advance notification signals to receiving circuits before data transfer. This allows receiving circuits to prepare their data capture circuits in advance, knowing when to sample incoming data without requiring continuous clock synchronization.
Solution Approach 2:
The patent uses feedback protocols where receiving circuits send acknowledgment signals back to transmitting circuits, confirming when data has been successfully captured. This feedback mechanism simplifies the operation of asynchronous systems by providing explicit timing information without requiring complex synchronization logic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, area, and cost by enabling asynchronous operation while allowing synchronous data communication, providing a 'common clock' only when necessary, and matching delays in pipelines to ensure effective signal amplification and synchronization.
Implementation Method 1
proximity communication includes capacitively coupled proximity communication
Data Source
AI summary
An integrated circuit includes a first pipeline with multiple stages of asynchronous circuits. Note that a stage in the first pipeline communicates with a stage in a corresponding second pipeline with multiple stages of asynchronous circuits on another integrated circuit via connectors. Furthermore, a first state wire preceding the stage in the first pipeline provides advanced notice to a first state wire preceding the stage in the second pipeline of subsequent communication between the stage in the first pipeline and the stage in the second pipeline so that the stage in the second pipeline has time to amplify a signal received from the stage in the first pipeline, thereby facilitating approximately synchronous operation of the stages in the first and second pipelines.