Asynchronous Interface Circuit for Test Data Transfer
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Solution Overview
Problem
Interfacing asynchronous clock domains for circuit test presents challenges due to differences in clock speeds and phase relationships, leading to interruptions in system function and high silicon area costs, as well as sensitivity to frequency ratios and duty cycles in existing solutions.
Innovation Solution
A configurable interfacing circuit with clock gating, transition detecting, and retiming devices that generate synchronized clock pulses across clock domains, using a delay generating device to adjust shift clock pulses based on frequency ratios, reducing sensitivity to clock frequency and duty cycle variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock substitution method is used to interface asynchronous clock domains, then data transfer between clock domains is enabled, but system function is interrupted during data transfer
Solution Approach 1:
The patent introduces a bridge circuit as an intermediary component that interfaces between the TAP clock domain and the system clock domain. This bridge circuit includes retiming registers and control logic that enable asynchronous data transfer without requiring the system to stop functioning, thus resolving the contradiction between reliable data transfer and continuous system operation.
2Reliability
If clock substitution method is used, then data transfer across clock domains is achieved, but PLL resynchronization takes a long time
Solution Approach 1:
The bridge circuit performs preliminary retiming of data using retiming registers before data enters the system clock domain. This preliminary action prepares the data in advance with proper timing relationships, eliminating the need for lengthy PLL resynchronization that would otherwise be required after clock substitution operations.
3Reliability
If shadow registers are used to interface asynchronous clock domains, then data transfer is enabled, but silicon area increases due to flip-flop duplication
Solution Approach 1:
The bridge circuit serves multiple functions within a compact structure: it performs retiming, level shifting, and protocol conversion between clock domains. By consolidating these functions into a single multi-functional component rather than duplicating flip-flops throughout the system, the patent reduces overall silicon area while maintaining reliable data transfer.
4Reliability
If existing asynchronous interface is used, then data transfer across clock domains is enabled, but the interface is sensitive to frequency ratio and duty cycle variations
Solution Approach 1:
The bridge circuit incorporates dynamic control logic that automatically adjusts its operation based on the actual clock frequency ratio and duty cycle conditions. The control logic monitors clock characteristics and dynamically configures the retiming registers and data transfer timing to maintain reliable operation across varying clock conditions, thus improving adaptability.
Data Source
AI summary
A circuit comprises: a first clock gating device clocked by a first clock signal and configured to generate first clock pulses when a shift enable signal is active, a first transition detecting device clocked by a second clock signal and configured to generate shift gating pulses when detecting active transitions of the first clock pulses, a second clock gating device clocked by the second clock signal and configured to generate shift clock pulses based on the shift gating pulses to clock second scan elements for a shift operation with first scan elements clocked by the first clock signal, and a first retiming device triggered by active pulse edges of the first clock signal and configurable to hold a value for the shift operation. The circuit may further comprise a delay generating device configured to generate delayed shift gating pulses for generating the shift clock pulses.