Asynchronous Interface Circuit Data Transfer Clock Domain
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Solution Overview
Problem
Asynchronous interface circuits face challenges in data transfer due to differences in clock domains between source and destination, leading to difficulties in capturing data in a timed manner, especially when the last data is not transferred correctly in two-stage data transmission processes.
Innovation Solution
An asynchronous interface circuit with a data holding circuit, an asynchronous memory, a monitor for detecting the operating state, and a selector to choose between data from the memory and the holding circuit based on the monitor's detection, ensuring data is transferred in synchronism with different clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer is performed in two stages through FIFO buffer, then data transfer between different clock domains is enabled, but the last data may not be transferred correctly when clock signal is lost
Solution Approach 1:
The patent introduces a monitor circuit as an intermediary between the FIFO buffer and the data output stage. This monitor detects the operating state of the FIFO and generates control signals to ensure the last data is properly transferred. The intermediary resolves the contradiction by adding control logic that prevents data loss without blocking the two-stage transfer mechanism.
Solution Approach 2:
The monitor circuit implements a feedback mechanism by continuously detecting the FIFO's operating state (empty, full, or intermediate) and using this information to control the data output timing. The feedback ensures that when the clock signal is lost or the last data arrives, the system can detect this state and adjust the output timing accordingly, preventing data loss while maintaining normal two-stage transfer operation.
2Adaptability or versatility
If clock transfer is performed using FIFO buffer, then asynchronous data transfer is enabled, but timing synchronization becomes difficult when delay exceeds clock cycle
Solution Approach 1:
The monitor circuit performs self-service by automatically detecting the FIFO's operating state and generating the necessary control signals without external intervention. This self-monitoring capability allows the system to adapt to varying delay conditions (0-20 nsec) and clock domain differences automatically, making the asynchronous interface easier to operate while maintaining broad compatibility.
Solution Approach 2:
The system performs preliminary action by pre-detecting the FIFO's state before data output is attempted. The monitor continuously monitors the FIFO status in advance, so when the last data arrives or clock signal is lost, the control logic is already prepared to adjust the output timing. This preliminary detection prevents timing synchronization issues before they occur.
Data Source
AI summary
An asynchronous interface circuit for transferring a data stream between different clock domains, the asynchronous interface circuits includes a data holding circuit for sequentially receiving and transferring data of the data stream in synchronism with a first clock signal, and holding the received data until an input of a next data, an asynchronous memory for sequentially receiving the data held in the data holding circuit in synchronism with the first clock signal and for outputting the data in the order of inputting in synchronism with a second clock signal. The asynchronous interface circuit further includes a monitor for detecting an operating state of the asynchronous memory, and a selector for selecting one of the data output from the asynchronous memory and the data output from the data holding circuit on the basis of a detecting result of the monitor.