Synchronous to Asynchronous Logic Conversion via Automated Synthesis
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Solution Overview
Problem
The implementation of asynchronous circuit designs is often hindered by the requirement for extensive time, experience, and dedicated tools, making it difficult to adopt in Application Specific Integrated Circuit (ASIC) devices, which predominantly use synchronous circuits and techniques.
Innovation Solution
The development of methods and apparatus that automatically synthesize synchronous logic described in Hardware Description Language (HDL) using automated substitution with a library of asynchronous standard cell components, allowing for the conversion of synchronous logic to asynchronous logic, thereby leveraging the benefits of asynchronous designs without the complexities of first-principles asynchronous implementations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If asynchronous circuit designs are implemented from first principles, then performance and power benefits are achieved, but design complexity and required expertise increase significantly
Solution Approach 1:
The patent introduces an automatic synthesis tool as an intermediary that translates synchronous HDL code into asynchronous circuit implementations. This mediator handles the complexity of asynchronous design internally, allowing designers to write simple synchronous code while the tool generates the optimized asynchronous circuit, thus achieving power benefits without increasing design complexity
Solution Approach 2:
The patent replaces the manual mechanical process of asynchronous circuit design with an automated computer-based synthesis system. The synthesis tool automatically performs the complex transformations from synchronous to asynchronous logic, eliminating the need for designers to manually create complex asynchronous circuits while still achieving the power efficiency benefits
2Speed
If asynchronous circuit designs are implemented from first principles, then performance benefits are achieved, but design time and required tools increase significantly
Solution Approach 1:
The patent performs preliminary automatic synthesis and optimization of asynchronous circuits before implementation. The synthesis tool pre-processes the synchronous HDL code, automatically generates the asynchronous circuit architecture, and optimizes it for performance, eliminating the need for time-consuming manual design iterations while achieving high-performance asynchronous circuits
3Ease of manufacture
If synchronous circuits are used in ASIC devices, then ease of design and existing tool compatibility are maintained, but performance and power benefits of asynchronous designs are lost
Solution Approach 1:
The patent changes the fundamental parameter of circuit timing from synchronous (clock-driven) to asynchronous (event-driven) while maintaining ease of design through automatic synthesis. The tool automatically handles the parameter transformation from synchronous HDL descriptions to asynchronous implementations, allowing designers to maintain simple design workflows while achieving the power efficiency benefits of asynchronous circuits
Data Source
AI summary
Apparatus, systems, and methods may operate to generate a synchronous netlist from a synchronous circuit design representation, automatically substitute asynchronous components taken from an asynchronous standard cell component library for corresponding standard cell synchronous components in the synchronous netlist to form an asynchronous core, and convert the synchronous netlist to an asynchronous circuit design representation. Additional apparatus, systems, and methods are disclosed.