Asynchronous Multiplier-Accumulator Using Charge Transfer Lines
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Solution Overview
Problem
Existing multiplier-accumulator architectures for machine learning applications face high power dissipation due to synchronous clocked operations and increased gate complexity, particularly in scalable hardware designs for multiply-accumulate operations.
Innovation Solution
An asynchronous multiplier-accumulator architecture utilizing AND gates and charge transfer capacitors to minimize internal state changes, allowing for asynchronous operation and reduced power consumption by sharing analog charge lines and using binary-weighted charge summing capacitors for efficient charge transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If synchronous clocked stages are used for multiplier operation, then operation timing is controlled, but power dissipation increases
Solution Approach 1:
The patent transitions from static synchronous clocked operation to dynamic asynchronous operation. The multiplier operates without a global clock, allowing each operation to proceed at its own pace based on input data availability. This dynamic approach eliminates continuous clock signaling and associated power dissipation while maintaining operational control through handshaking protocols between stages.
Solution Approach 2:
The patent extracts and removes the global clocking mechanism from the multiplier architecture. By taking out the synchronous clock signal and replacing it with asynchronous control signals generated locally at each stage, the design eliminates the primary source of dynamic power consumption associated with clock distribution and edge-triggered flip-flop operations.
2Productivity
If large n×n multiplier size is increased for machine learning applications, then computational capability improves, but gate complexity increases as n2
Solution Approach 1:
The patent segments the large n×n multiplication operation into multiple smaller partial product generations. Instead of generating all n2 product terms simultaneously, the architecture divides the computation into stages where partial products are generated incrementally and accumulated. This segmentation reduces the peak gate complexity at any given moment while maintaining the overall computational capability for large matrix operations.
Solution Approach 2:
The patent introduces a temporal dimension to the multiplication process by using asynchronous operation. Rather than computing all partial products in parallel within a single clock cycle (spatial dimension only), the design allows partial products to be generated and accumulated over multiple time steps. This dimensional transformation reduces spatial gate complexity by distributing computations across time, enabling large n×n multipliers to operate with manageable instantaneous complexity.
3Measurement precision
If many adders are used for multiply-accumulate operations, then computational accuracy improves, but power consumption increases
Solution Approach 1:
The patent merges the multiplication and accumulation operations into a unified asynchronous multiplier-accumulator architecture. Instead of separating multiply and add operations into distinct stages with multiple adders, the design combines these functions so that partial products are generated and accumulated in an integrated manner. This merging reduces the total number of adder circuits required while maintaining computational accuracy through the asynchronous accumulation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables low-power, scalable, and efficient multiply-accumulate operations by minimizing internal state changes and power consumption, particularly when dealing with static weighting matrices in machine learning calculations, while maintaining flexibility for various matrix sizes.
Implementation Method 1
each AND gate output coupled to an analog charge line associated with the bit order through a charge transfer capacitor of value Cu
Implementation Method 2
the charge summing unit comprising charge summing capacitors which provide a charge transfer for each analog charge line of two to the power of the bit order
Data Source
AI summary
A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.