Asynchronous Memory Control Logic for Lower Clock Routing Power
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Solution Overview
Problem
The existing memory devices consume significant power due to long global clocks and buses in their control logic circuits, leading to inefficient power usage.
Innovation Solution
Implementing an asynchronous control logic that generates local clock signals through a handshaking protocol, eliminating the need for global clocks and buses, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If global clocks and buses are used for control logic circuit interaction, then control signals can be transmitted across the memory device, but power consumption increases significantly due to long routing paths
Solution Approach 1:
The control logic circuit is divided into multiple independent modules (decoder module, control register module, state machine module) that can operate autonomously. Each module has its own local control signals and registers, eliminating the need for long global clock and bus routing. The segmentation allows each module to process control signals locally, reducing the routing length and associated power consumption while maintaining overall system functionality.
Solution Approach 2:
Handshaking signals (REQ/ACK) are introduced as intermediaries between control modules to enable asynchronous communication without global clocks. The request-acknowledge mechanism allows modules to coordinate their operations through localized signal exchange, replacing the need for power-consuming global timing signals while ensuring proper synchronization of control operations.
2Reliability
If global clocks are used for synchronization, then all control modules can operate in sync, but the long clock routing consumes excessive power
Solution Approach 1:
Handshaking signals (REQ/ACK) serve as intermediaries for inter-module communication, enabling reliable coordination without global clocks. The request-acknowledge protocol ensures that control operations are properly synchronized through localized signal exchange between modules, maintaining reliability while eliminating power-consuming global clock distribution.
Solution Approach 2:
The control system transitions from static global clock synchronization to dynamic asynchronous handshaking. Each module can proceed with operations when ready, using dynamic REQ/ACK signal exchange to coordinate timing. This dynamic approach maintains synchronization reliability while adapting to varying operational requirements without the overhead of continuous global clock signaling.
3Use of energy by stationary object
If asynchronous control logic with local clock signals is implemented, then power consumption is reduced by eliminating global clocks, but control module coordination becomes more complex
Solution Approach 1:
The control logic is segmented into independent modules with well-defined interfaces using handshaking protocols. This segmentation reduces overall complexity by allowing each module to be designed and verified independently, with standard REQ/ACK interaction patterns. The modular structure makes the system more manageable despite the asynchronous nature, as each segment handles only local coordination rather than global synchronization.
Solution Approach 2:
The control mechanism changes from time-based global clock synchronization to event-based handshaking signals. This parameter change fundamentally simplifies the coordination complexity by replacing continuous clock monitoring with discrete request-acknowledge events. The complexity shifts from timing-critical global synchronization to simpler local event-driven coordination, reducing the overall control logic burden.
Data Source
AI summary
A memory device includes a memory array configured to store data, and a peripheral circuit coupled to the memory array and including a control logic circuit to control operations of the peripheral circuit. The control logic circuit includes a main control circuit and at least one first sub control circuit, and the main control circuit and the first sub control circuit interact through a first trigger signal and a first indication signal. The main control circuit and the first sub control circuit interact through an asynchronous control logic without a global clock signal.