Asynchronous Memory Module with DRAM Cache for Latency Optimization
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Solution Overview
Problem
Current DDR4-based memory systems face challenges in efficiently managing and accessing data between non-volatile dual in-line memory modules (NVDIMMs) and standard DRAMs, particularly in maintaining backward compatibility and optimizing latency, especially when operating in cache modes.
Innovation Solution
A DDR-compatible asynchronous memory module system that includes a non-volatile memory with a DRAM cache, a data buffer, and a registering clock driver (RCD) with control and address buffers, enabling asynchronous access to non-volatile memory and synchronous access to DRAM cache, through a DDR interface and message interface with a host memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If NVDIMM operates in cache mode with DRAM, then data access speed is improved, but system complexity increases due to dual memory management
Solution Approach 1:
The memory system is segmented into two distinct access paths: a synchronous path for DRAM cache access and an asynchronous path for NVM access. The memory controller divides memory addresses into cache addresses and storage addresses, routing them through different interfaces. This segmentation allows fast DRAM access for frequently used data while maintaining backward compatibility with existing DDR4 systems, resolving the contradiction between speed improvement and system complexity.
2Loss of time
If asynchronous access to non-volatile memory is implemented, then latency is reduced, but interface compatibility becomes more difficult to maintain
Solution Approach 1:
A dual-interface memory controller is introduced as an intermediary between the host and the memory modules. The controller provides a synchronous DDR4 interface to the host for backward compatibility, while simultaneously providing an asynchronous interface to the NVM. The controller translates and manages data transfer between these interfaces, reducing access latency for NVM operations while maintaining compatibility with existing DDR4 memory systems.
3Productivity
If DRAM cache is directly accessible by host controller, then handshaking overhead is eliminated, but data consistency between DRAM and NVM becomes more challenging
Solution Approach 1:
The memory controller implements feedback mechanisms to maintain data consistency between DRAM cache and NVM. When data is written to the DRAM cache, the controller tracks these writes and provides feedback to the NVM management logic. This ensures that cached data is eventually synchronized with persistent storage, maintaining data consistency while allowing direct access to the DRAM cache without handshaking overhead.
Data Source
AI summary
A method includes: providing a DDR interface between a host memory controller and a memory module; and providing a message interface between the host memory controller and the memory module. The memory module includes a non-volatile memory and a DRAM configured as a DRAM cache of the non-volatile memory. Data stored in the non-volatile memory of the memory module is asynchronously accessible by a non-volatile memory controller of the memory module, and data stored in the DRAM cache is directly and synchronously accessible by the host memory controller.