Asynchronous Memory Scan Scheduling for Host Performance
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Solution Overview
Problem
In systems with multiple memory subsystems, synchronous scan operations across these subsystems can lead to periodic performance degradations for host systems due to simultaneous data integrity checks, which are necessary to prevent data corruption but can interfere with host-initiated operations.
Innovation Solution
Implementing asynchronous scan operations by varying the initiation delay of scan operations across memory subsystems, using a unique delay value for each subsystem, which can be preprogrammed, self-generated, or specified by the host system, to reduce the likelihood of simultaneous scans and minimize performance impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous scan operations are performed across multiple memory subsystems, then data integrity is ensured through coordinated data integrity checks, but host system performance degrades due to simultaneous scans interfering with host-initiated operations
Solution Approach 1:
The patent implements periodic scan operations with varying periods across different memory subsystems. Each memory subsystem performs scan operations at different time intervals rather than simultaneously, which ensures data integrity through regular scans while reducing performance degradation by distributing the scan load over time. The controller configures different scan periods for different memory subsystems to achieve this asynchronous periodic action.
Solution Approach 2:
The patent introduces dynamic timing configuration where the scan operation timing is not fixed but can be adjusted and varied across different memory subsystems. The controller dynamically assigns different delay values and scan periods to different memory subsystems, making the scan schedule flexible and adaptive rather than rigid and synchronous, thereby balancing data integrity requirements with host performance needs.
2Reliability
If scan operations are performed frequently to prevent data corruption, then data reliability improves, but the performance impact on host system operations increases
Solution Approach 1:
The patent implements periodic scan operations where scans are performed at regular intervals rather than continuously or frequently. By configuring appropriate scan periods, the system maintains data reliability through regular integrity checks while avoiding excessive scans that would degrade host performance. The periodic nature allows host operations to proceed uninterrupted between scan cycles.
Solution Approach 2:
The patent applies partial action by performing scans on a selective and distributed basis rather than uniformly across all memory subsystems at all times. Different memory subsystems undergo scanning at different frequencies and times, which provides sufficient data reliability for each subsystem without the excessive performance penalty that would result from frequent simultaneous scans across all subsystems.
3Reliability
If multiple memory subsystems perform scan operations simultaneously, then data integrity checking is maximized, but system performance degrades due to resource contention
Solution Approach 1:
The patent implements periodic scan operations with different periods for different memory subsystems, ensuring that data integrity checking is performed regularly across all subsystems but not simultaneously. This distributed periodic approach maximizes overall data integrity monitoring while avoiding the performance degradation that would result from simultaneous scans consuming shared system resources.
Solution Approach 2:
The patent segments the scan operation scheduling across multiple memory subsystems, dividing the overall scanning task into separate, non-overlapping time segments for each subsystem. This segmentation ensures comprehensive data integrity checking across all subsystems while distributing resource usage over time, thereby preventing resource contention and performance degradation that would occur with simultaneous scans.
Data Source
AI summary
A first delay value is obtained by a first memory subsystem of a plurality of memory subsystems. The first memory subsystem performs a first scan operation after a first time from a first event for the first memory subsystem. The first time is based on the first delay value. A second memory subsystem of the plurality of memory subsystems performs a second scan operation based upon a second delay value that is different than the first delay value.