Asynchronous Memory Control via Data Tracking Signal
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Solution Overview
Problem
Conventional high-performance memory systems face limitations in data access frequency due to synchronous operations, leading to increased size, cost, and power consumption of peripheral circuitry, necessitating a novel memory architecture and transmission interface protocol to optimize bandwidth and power consumption.
Innovation Solution
An asynchronous control method for memory devices that performs data access operations independently of the system clock, using a data tracking signal to synchronize data transmission between the memory device and the memory control unit, eliminating the need for complex peripheral circuits like FIFO and PLL, and enabling high-speed data read/write transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If synchronous operation is used to achieve high data access frequency, then data access frequency is improved, but peripheral circuitry size and power consumption increase
Solution Approach 1:
The patent extracts the clock synchronization function from the memory device itself and relocates it to the memory controller. The memory device operates asynchronously without internal PLL circuits, while the memory controller generates clock signals and manages timing for multiple memory devices. This extraction eliminates the need for complex peripheral circuitry in each memory device while maintaining high data access frequency through centralized clock management.
2Productivity
If synchronous operation with PLL circuits is used to maintain clock synchronization, then data access frequency is improved, but power consumption increases
Solution Approach 1:
The patent removes PLL circuits from individual memory devices, extracting the clock generation and synchronization functions to the memory controller. This eliminates the power consumption associated with multiple PLL circuits in each memory device while maintaining high-speed operation through centralized clock management in the controller.
Solution Approach 2:
The memory controller serves as a universal clock management unit that handles timing and synchronization for multiple memory devices simultaneously. This multi-functional approach replaces the need for dedicated PLL circuits in each memory device, reducing overall power consumption while maintaining high data access frequency across the system.
3Device complexity
If asynchronous operation is used to simplify memory device architecture, then device complexity is reduced, but data access frequency decreases
Solution Approach 1:
The patent introduces the memory controller as an intermediary that manages timing and coordination between the asynchronous memory devices and the system. The controller generates clock signals and controls the timing of read/write operations, enabling high data access frequency without requiring the memory devices themselves to be synchronous. This intermediary approach allows memory devices to remain simple and asynchronous while achieving high-speed operation through external coordination.
Data Source
AI summary
A control method of a memory device, a memory device and a memory system are provided. The memory system includes a memory control unit and a memory die. The memory die performs a data access operation asynchronously with respect to a system clock according to address information and an access signal generated from the memory control unit. When operating in a read mode, the memory die generates a data tracking signal according to a memory internal read time which is an elapsed time for data to be read to be read out from the memory die. The memory control unit and the memory die obtain required data according to respective data tracking signals transmitted therebetween. The control method defines an asynchronous memory interface protocol which realizes reliable and high speed data transmission.