Async Multi-Plane Reading for Memory System Firmware Loading
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Solution Overview
Problem
Existing memory systems face challenges in efficiently performing read and write operations, particularly due to the large storage capacity requirements of firmware code, which leads to prolonged loading times and reduced performance.
Innovation Solution
The proposed memory system employs an async multi-plane independent reading operation to simultaneously read code data from multiple code blocks stored across different memory planes, allowing for the construction of complete firmware code in fewer read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If firmware code is stored in traditional sequential reading manner, then storage capacity is sufficient, but loading time is prolonged and performance is reduced
Solution Approach 1:
The patent divides firmware code into multiple code blocks and distributes them across different memory planes. Each plane can be read independently and simultaneously, transforming a single sequential reading process into multiple parallel reading processes. This segmentation of code blocks across planes enables concurrent access and significantly reduces the total loading time while improving system performance.
2Productivity
If code data is read from multiple memory planes simultaneously, then reading performance is improved, but device complexity increases
Solution Approach 1:
The patent implements an async multi-plane independent reading operation mechanism that enables the memory system to simultaneously read from multiple planes using the same reading circuitry. This multi-functionality approach allows a single reading mechanism to handle multiple planes in parallel through asynchronous operations, improving reading performance without proportionally increasing device complexity.
Data Source
AI summary
Examples of the present disclosure provide a memory system and an operation method thereof. The memory system comprises: a memory device and a memory controller coupled to the memory device; wherein, the memory device comprises at least one memory die, and the memory die comprises a plurality of code blocks storing code data; the code data stored in the plurality of code blocks is identical; the memory die comprises a plurality of memory planes, and the plurality of code blocks are stored in different memory planes; the memory controller is configured to: read a portion of code data of each code block of at least a portion of code blocks simultaneously by using an async multi-plane independent reading operation, wherein the read portion of code data of each code block constitutes complete code data stored in one code block.