Asynchronous On-Chip Router Using Handshake-Based Packet Routing
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Solution Overview
Problem
Conventional on-chip network (NoC) routers are synchronous, leading to high latency and energy consumption due to clock synchronization requirements, which affects system performance in devices like GPUs and CPUs.
Innovation Solution
Implementing an asynchronous router within network nodes that operates without a clock signal, utilizing a four-phase handshake protocol to reduce routing latency and power consumption by allowing packet transmission in less than one clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If synchronous routers are used in network nodes, then routing control and arbitration can be implemented systematically, but routing latency increases to 1-10 clock cycles
Solution Approach 1:
The routing function is segmented into separate components: input ports, output ports, and routing logic. Each input port independently determines routing destination and asserts route requests to selected output ports, eliminating the need for centralized arbitration and reducing latency.
Solution Approach 2:
Instead of using a centralized controller to arbitrate routing decisions (conventional approach), the patent inverts the control flow by allowing input ports to directly control output port selection through asserted route requests, eliminating the arbitration bottleneck.
2Use of energy by stationary object
If synchronous clock signaling is used, then system coordination is simplified, but energy consumption increases due to clock distribution
Solution Approach 1:
The clock signal is extracted and removed from the routing system. The patent uses asynchronous handshake protocols between input and output ports, eliminating the need for clock distribution networks and associated energy consumption while maintaining reliable coordination through request-acknowledge sequences.
3Adaptability or versatility
If more input ports are connected to each output port, then routing flexibility increases, but arbitration complexity and latency increase
Solution Approach 1:
Each input port independently determines its own routing destination and directly asserts route requests to the appropriate output ports without requiring arbitration. This self-service approach maintains routing flexibility while eliminating arbitration latency.
Data Source
AI summary
An on-chip network (NoC) is a critical component of a GPU, CPU, network switch, or accelerator. The network nodes may be arranged in a two-dimensional array with each network node coupled to neighboring network nodes vertically and horizontally, with or without diagonal connections. Conventional routers within network nodes are synchronous, taking from 1-10 clock cycles to determine an output port, arbitrate between virtual and physical channels, and account for credits. In contrast, in an embodiment, transmission of a packet between network nodes often occurs in less than one clock cycle because the handshake protocol and the circuitry are not synchronized using a clock signal. When implemented using asynchronous logic, the routing delay and power are reduced. The channel latency is the minimum time needed to drive the physical traces. Such an asynchronous NoC may reduce latency by a factor of two or more compared with a synchronous NoC.