Asynchronous Phase Sampling in Frequency-to-Digital PLL Conversion
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Solution Overview
Problem
Current digital fractional-N PLLs face challenges with tight timing constraints and high sensitivity to non-ideal frequencies, leading to increased power consumption, circuit complexity, and phase noise, especially at higher bandwidths.
Innovation Solution
The implementation of a delta-sigma frequency-to-digital converter with digital background calibration and a simplified architecture that dynamically adjusts digital circuitry to compensate for frequency errors, reducing the need for complex analog adjustments and improving phase noise performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If digital fractional-N PLLs are used to avoid large analog loop filters, then device leakage and low supply voltages are tolerated better, but quantization noise has higher power or higher spurious tones leading to worse phase noise performance
Solution Approach 1:
The patent replaces the traditional mechanical/analog phase-frequency detector and charge pump system with a fully digital frequency-to-digital converter that directly measures frequency and converts it to digital values. This substitution eliminates the quantization noise and spurious tones inherent in digital fractional-N PLLs while maintaining compatibility with scaled CMOS technology and low supply voltages, thereby resolving the contradiction between adaptability and phase noise performance
Solution Approach 2:
The patent introduces an asynchronous phase sampler as an intermediary component between the dual-mode ring oscillator and the digital circuitry. This sampler accurately captures phase information without introducing quantization noise, serving as a mediator that preserves signal integrity while enabling fully digital implementation, thus improving phase noise performance without sacrificing adaptability
2Measurement precision
If tight timing constraints are imposed to handle non-ideal frequencies, then frequency accuracy is improved, but power consumption and circuit complexity increase
Solution Approach 1:
The patent employs a dual-mode ring oscillator that can dynamically switch between two operating modes to handle non-ideal frequencies. This dynamic adaptation allows the system to maintain frequency accuracy without imposing tight timing constraints, thereby avoiding increased circuit complexity and power consumption while preserving measurement precision
Solution Approach 2:
The patent changes the operating parameters of the frequency-to-digital converter by using an asynchronous sampling approach rather than synchronous sampling. This parameter change allows the system to accommodate non-ideal frequencies and variations without requiring tight timing constraints, thus maintaining frequency accuracy while reducing circuit complexity
3Measurement precision
If tight timing constraints are imposed to handle non-ideal frequencies, then frequency accuracy is improved, but power consumption increases
Solution Approach 1:
The dual-mode ring oscillator dynamically adjusts its operation to handle non-ideal frequencies without requiring tight timing constraints. This dynamic behavior enables the system to maintain frequency accuracy while avoiding the high power consumption that would result from enforcing strict timing requirements
Solution Approach 2:
The asynchronous phase sampler automatically adapts to the actual timing of oscillator edges without requiring external timing control or synchronization. This self-service approach allows the system to maintain frequency accuracy while minimizing power consumption by avoiding the overhead of tight timing management
4Speed
If higher bandwidth is implemented in digital PLLs, then response speed is improved, but phase noise performance deteriorates
Solution Approach 1:
By replacing the traditional phase-frequency detector and charge pump with a frequency-to-digital converter, the patent eliminates the quantization noise that typically deteriorates with higher bandwidth. This substitution allows the system to achieve fast response speed while maintaining excellent phase noise performance, resolving the contradiction between speed and reliability
Data Source
AI summary
A ΔΣ frequency to digital converter includes digital feedback to an accumulator in a ring phase calculator that provides the converter output, which reduces implantation complexity. Digital gain correction is applicable to dual mode ring oscillator converters and charge pump converters, provides compensation for forward path gain error and eliminates the need to include analog gain correction in feedback. Asynchronous sampling includes correction logic to compensate for arbitrary initial conditions. A digitally-controlled oscillator (DCO) control technique causes the DCO frequency to increase or decrease by changing the state of one its frequency control elements at a time.