Asynchronous Pipelined Interconnect with Fanout Support

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Solution Overview

Problem

Clocked FPGAs face issues with delay variation, energy inefficiency, and increased power consumption due to the need for global retiming and continuous clock pulse activation, while asynchronous pipelined interconnects lack fan out support, leading to reduced processing speed and increased die area.

Innovation Solution

The implementation of asynchronous programmable interconnects with buffer-switch circuits that support fan out by using multi-port switch points and programmable completion detection elements, allowing for flexible and efficient connectivity between ports without a global clock, reducing power consumption and die area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If asynchronous pipelined interconnects are used, then power consumption and die area are reduced, but fan out support is lost leading to reduced processing speed

Engineering Contradiction:

Improvepower consumptionVSAvoidprocessing speed

Core Design Contradiction:

Use of energy by stationary objectVSProductivity

Solution Approach 1:

The interconnect is divided into multiple pipeline stages with buffer-switch circuits at each stage. Each stage independently handles a portion of the data transmission, allowing fan out operations to be performed at specific stages without blocking the entire pipeline. This segmentation enables parallel processing of data at different stages, maintaining processing speed while using asynchronous operation to reduce power consumption.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Buffer-switch circuits are pre-configured with switch points that can be programmed to enable fan out support before data arrives. The completion detection elements are pre-positioned to anticipate when data transmission is complete, allowing the system to prepare for the next operation in advance. This preliminary configuration reduces waiting time and maintains high processing speed despite the added fan out capability.

Inventive Principle:

Principle #10Preliminary action

2Adaptability or versatility

If clocked FPGAs with global retiming are used, then connectivity flexibility is improved, but energy inefficiency and power consumption increase

Engineering Contradiction:

Improveconnectivity flexibilityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

The global clock signal and global retiming mechanism are completely removed from the system. Instead, asynchronous handshaking signals are used at each local buffer-switch circuit to coordinate data transmission. This extraction of the global clock eliminates the continuous power consumption associated with clock distribution and retiming operations, while local asynchronous control maintains connectivity flexibility through programmable switch points.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

Each buffer-switch circuit autonomously manages its own data transmission using local handshaking signals and completion detection elements. The circuits self-coordinate without requiring external clock synchronization, allowing each element to operate independently and efficiently. This self-service approach eliminates the energy overhead of global clocking while maintaining flexible connectivity through local decision-making.

Inventive Principle:

Principle #25Self-service

3Productivity

If buffer-switch circuits with fan out support are added, then processing speed and connectivity are improved, but device complexity increases

Engineering Contradiction:

Improveprocessing speedVSAvoidcircuit complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The buffer-switch circuit is designed as a universal element that can perform multiple functions: standard data transmission, fan out to multiple destinations, and completion detection. The same switch points and buffer elements are reconfigured based on operational requirements rather than having separate dedicated circuits for each function. This multi-functionality reduces the overall number of discrete components needed, managing device complexity while enabling enhanced processing speed and connectivity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The switch points, buffer circuits, and completion detection elements are merged into a single integrated buffer-switch circuit module. Rather than implementing fan out support as a separate add-on component, the detection elements are combined with the existing switch fabric. This integration shares common resources and control logic, reducing the complexity overhead that would result from completely separate implementations of each function.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS9344385B2Asynchronous pipelined interconnect architecture with fanout support

Publication Date: 2016.05.17 ACHRONIX SEMICONDUCTOR CORP

AI summary

Circuits comprising an asynchronous programmable interconnect with fan out support that include a multi-port switch and a first and second buffer-switch circuit, and methods of forming such circuits, are provided. Additional circuits and methods are disclosed.