Asynchronous Processor Pipelined Arithmetic Logic Unit Latency Reduction
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Solution Overview
Problem
Existing asynchronous processor architectures face latency issues due to the need for non-standard Muller-C elements in handshaking protocols, which are challenging to implement and lead to increased computation delays.
Innovation Solution
The proposed solution involves a token-based pipelined architecture where instruction execution units (XUs) in a ring configuration manage tokens to control access to resources without clock synchronization, allowing for the execution of subsequent instructions before releasing previous ones, thereby reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional asynchronous processor architecture with Muller-C elements is used, then handshaking protocol between computing logic stages is achieved, but computation latency increases and implementation complexity increases
Solution Approach 1:
The patent implements a token-based system where tokens are pre-positioned in pipeline stages before actual data processing. The token at stage N+1 is ready to grant access to the next stage before the current instruction completes, allowing the next instruction to be launched in advance without waiting for commit token release, thus reducing computation latency while maintaining protocol correctness
Solution Approach 2:
The patent divides the pipeline into distinct stages with independent token control. Each pipeline stage has its own token that can be independently managed, allowing parallel progression of multiple instructions through different stages. This segmentation enables overlapping execution of instructions without requiring sequential token release, reducing overall latency
2Reliability
If traditional asynchronous processor architecture with Muller-C elements is used, then handshaking protocol between computing logic stages is achieved, but device complexity increases
Solution Approach 1:
The patent replaces complex non-standard Muller-C elements with simplified token processing logic that uses standard digital logic components. The token-based handshaking mechanism is implemented using conventional logic gates and flip-flops, making the design more implementable with standard technology while maintaining the reliability of the handshaking protocol
Solution Approach 2:
The patent introduces tokens as intermediary control signals that mediate between pipeline stages. These tokens act as simple binary flags that indicate readiness and permission, replacing the complex mutual exclusion logic of Muller-C elements. The token processing logic uses straightforward state machines that are easier to implement and verify than traditional asynchronous handshaking circuits
3Ease of operation
If token-based pipelining with sequential execution is used, then resource access control is achieved, but processor performance decreases
Solution Approach 1:
The patent allows tokens for subsequent instructions to be fetched and positioned in advance in the pipeline stages before the previous instruction releases its commit token. This preliminary positioning of tokens enables the next instruction to immediately begin execution when ready, eliminating idle cycles and improving processor performance while maintaining controlled resource access
Solution Approach 2:
The patent ensures continuous pipeline operation by allowing multiple instructions to be in different pipeline stages simultaneously, each with its own token. The pipeline maintains continuous flow of work through overlapping instruction execution, preventing idle stages and maximizing processor utilization while preserving ordered resource access through token sequencing
Data Source
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AI summary
Embodiments are provided for an asynchronous processor with pipelined arithmetic and logic unit. The asynchronous processor includes a non-transitory memory for storing instructions and a plurality of instruction execution units (XUs) arranged in a ring architecture for passing tokens. Each one of the XUs comprises a logic circuit configured to fetch a first instruction from the non-transitory memory, and execute the first instruction. The logic circuit is also configured to fetch a second instruction from the non-transitory memory, and execute the second instruction, regardless whether the one of the XUs holds a token for writing the first instruction. The logic circuit is further configured to write the first instruction to the non-transitory memory after fetching the second instruction.