Asynchronous Reset Logic Scan Testing
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Solution Overview
Problem
Existing scan test circuits face challenges in achieving high fault coverage for integrated circuits due to glitches caused by asynchronous reset signals, which can lead to unpredictable behavior and reduced test robustness, especially in the presence of metastability and cascaded reset signals.
Innovation Solution
The implementation of test circuitry using OR-AND-OR logic circuits combined with multiplexers and reset synchronizers to selectively deliver and mask asynchronous reset signals, preventing glitches during scan testing by enabling synchronous and asynchronous scan tests independently, and providing observation paths to monitor the functionality of reset signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If asynchronous reset signals are used in scan test circuits, then the circuit can be reset without clock dependency, but glitches and metastability occur causing unpredictable behavior
Solution Approach 1:
A test control block is introduced as an intermediary component that mediates between the asynchronous reset signal source and the scan test circuitry. This block selectively masks or delivers reset signals based on test mode, preventing direct asynchronous reset during scan operations while maintaining the ability to perform asynchronous reset testing when needed.
Solution Approach 2:
The reset signal delivery mechanism is made dynamic through the use of multiplexers and selective masking controlled by test mode signals. The circuit can switch between different reset signal paths depending on whether scan testing or functional testing is being performed, allowing optimal behavior for each test mode.
2Reliability
If asynchronous reset signals are delivered during scan testing, then reset functionality is maintained, but fault coverage is reduced due to glitches
Solution Approach 1:
The testing process is segmented into distinct modes: scan testing mode and asynchronous reset testing mode. During scan testing, reset signals are masked to prevent glitches and ensure high fault coverage. During dedicated reset testing, the masking is removed to test reset functionality. This segmentation allows each test type to optimize for its specific purpose.
Solution Approach 2:
Instead of completely disabling reset functionality during scan testing, the patent applies partial masking that selectively blocks reset signals only when they would cause harmful glitches during scan operations. The masking is controlled and reversible, allowing reset functionality to be partially maintained while preventing specific harmful effects.
3Reliability
If multiple asynchronous reset signals are cascaded, then reset coverage is improved, but metastability and unpredictable behavior increase
Solution Approach 1:
The test control block acts as a mediator that manages multiple cascaded reset signals. It selectively masks or delivers reset signals from different sources based on test requirements, preventing harmful interactions between cascaded reset signals during scan testing while allowing their effects to be tested independently when needed.
Data Source
AI summary
Testing of integrated circuitry, wherein the integrated circuitry includes a flip-flop with an asynchronous input, so that during performance of asynchronous scan patterns, glitches are avoided. Combinatorial logic circuitry delivers a local reset signal to the asynchronous input independent of an assertion of an asynchronous global reset signal. A synchronous scan test is performed of delivery of the local reset signal from the combinatorial logic circuitry while masking delivery of any reset signal to the asynchronous input of the flip-flop. An asynchronous scan test is performed of an asynchronous reset of the flip-flop with the asynchronous global reset signal while masking delivery of the local reset signal to the asynchronous input of the flip-flop.