Asynchronous Sample Rate Conversion for Jitter-Stable Audio Clocks
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Solution Overview
Problem
Mobile and consumer electronic devices face challenges in handling signals with arbitrary sample rates, leading to synchronization issues and 'glitches' due to asynchronous reference clocks, particularly in audio and video processing applications.
Innovation Solution
A sample rate converter is designed with a cross enable unit and a linear interpolation unit, incorporating a finite impulse response (FIR) filter module, sigma-delta loops, and a FIFO buffer to generate de-jittered and resampled clock signals, allowing for efficient conversion of input signals to stabilized output sample rates with minimal additional hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sample rate conversion is performed to handle asynchronous input signals with arbitrary sample rates, then signal synchronization and integrity are improved, but device complexity and computational requirements increase
Solution Approach 1:
The sample rate converter is divided into distinct functional modules: a cross enable unit for clock signal generation and a linear interpolation unit for signal resampling. This segmentation allows each module to perform its specific function efficiently, reducing overall system complexity while maintaining synchronization reliability.
Solution Approach 2:
The patent introduces an intermediate resampled clock signal as a mediator between the asynchronous input clock and the output signal. This intermediate clock serves as a bridge that enables smooth transition and synchronization without requiring complex direct conversion mechanisms.
2Reliability
If conventional sample rate conversion methods are used to handle frequency variations, then signal synchronization is maintained, but glitches occur in generated output signals when the sample stream clock changes or is removed
Solution Approach 1:
The cross enable unit generates the resampled clock signal in advance based on the input clock characteristics before the actual sample rate conversion occurs. This preliminary clock generation ensures that the linear interpolation unit has a stable reference signal ready, preventing glitches when the input clock changes or is removed.
Solution Approach 2:
The system monitors the input clock signal characteristics and uses this information to dynamically adjust the resampled clock signal generation. This feedback mechanism ensures continuous synchronization and prevents output glitches by adapting to clock variations in real-time.
3Adaptability or versatility
If multiple input signals with different sample rates are processed simultaneously, then signal processing versatility is improved, but computational complexity and hardware requirements increase
Solution Approach 1:
The sample rate converter is designed with universal functionality to handle multiple input signals with different sample rates using the same architectural framework. The cross enable unit and linear interpolation unit can process any number of asynchronous input signals by generating appropriate resampled clock signals for each, eliminating the need for separate conversion circuits for each signal.
Data Source
AI summary
An asynchronous sample rate converter and method for converting an input signal to a resampled output signal is disclosed. An efficient and cost-effective sample rate converter for converting an input signal of arbitrary sample rate to a resampled output signal of a second sample rate is disclosed. A hardware-efficient sample-rate converter for resampling an audio input signal with an arbitrary sample rate to an output audio signal with a known sample rate for use in an audio processor is disclosed.