Asynchronous Sampling Clock Gating for Data Rate Synchronization
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Solution Overview
Problem
Current asynchronous sampling technologies in communication systems are complex and power-intensive, making it challenging to achieve both power-saving and acceptable performance, especially when dealing with asynchronous clocks and frequency differences between systems.
Innovation Solution
An asynchronous sampling architecture that uses a gated clock generation unit to generate a gated clock with a frequency matching the peer end clock, allowing data to be read from a register without overflow or underflow, and incorporates Σ-δ modulation for simpler hardware and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asynchronous sampling rate converters are used to resample signals with local clock, then data rate synchronization is achieved, but hardware complexity and power consumption increase
Solution Approach 1:
The patent extracts only the essential function of asynchronous sampling rate conversion by using a simple register to buffer incoming data and a gated clock generation unit to control data output timing. This minimalistic approach achieves data rate synchronization without the complex hardware structures of conventional asynchronous sampling rate converters, directly resolving the contradiction between reliability and device complexity.
Solution Approach 2:
The patent introduces a gated clock generation unit as an intermediary component that mediates between the peer end clock and local clock. This unit generates a gated clock signal that controls the register output to match the local clock frequency, achieving asynchronous sampling rate conversion through a simple intermediary mechanism rather than complex hardware.
2Reliability
If asynchronous sampling rate converters are used to resample signals with local clock, then data rate synchronization is achieved, but power consumption increases
Solution Approach 1:
The patent extracts only the essential function of asynchronous sampling rate conversion by using a simple register to buffer incoming data and a gated clock generation unit to control data output timing. This minimalistic approach achieves data rate synchronization without the complex hardware structures of conventional asynchronous sampling rate converters, directly resolving the contradiction between reliability and device complexity.
Solution Approach 2:
The patent introduces a gated clock generation unit as an intermediary component that mediates between the peer end clock and local clock. This unit generates a gated clock signal that controls the register output to match the local clock frequency, achieving asynchronous sampling rate conversion through a simple intermediary mechanism rather than complex hardware.
3Device complexity
If simple register buffering is used without gated clock, then hardware complexity is reduced, but data overflow or underflow occurs
Solution Approach 1:
The patent introduces a gated clock generation unit as an intermediary component that mediates between the peer end clock and local clock. This unit generates a gated clock signal that controls the register output to match the local clock frequency, achieving asynchronous sampling rate conversion through a simple intermediary mechanism rather than complex hardware.
Solution Approach 2:
The gated clock generation unit employs periodic action by generating a gated clock signal that periodically enables or disables the register output based on the accumulated frequency difference between peer end clock and local clock. This periodic gating mechanism prevents data overflow or underflow while maintaining simple hardware structure.
Data Source
AI summary
The present application discloses an asynchronous sampling architecture and a chip. The asynchronous sampling architecture is configured to receive a first input data string from the peer end, and the asynchronous sampling architecture includes: a first register, configured to buffer a first input data string, wherein the first input data string is written into the first register according to a peer end clock of the peer end; and a gated clock generation unit, configured to generate a gated clock, wherein the frequency of the gated clock is the same as the frequency of the peer end clock, and the first input data string is read out as a first output data string from the first register according to the gated clock.