Asynchronous Sampling Interface Circuit for High-Skew Data Recovery
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Solution Overview
Problem
Conventional high-speed digital interface circuits face challenges in maintaining accurate data recovery due to high skews between data and clock channels, particularly in long transmission lines and varying transmission conditions, which are not effectively addressed by existing methods that rely on fixed sampling phase ratios and analog filter loops.
Innovation Solution
An asynchronous super sampling architecture is introduced, where the sampling clock is maintained independent of transmission frequency, allowing for flexible clock recovery from data channels and compensating phase variations digitally, without relying on fixed sampling phase ratios or analog filter loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If synchronous sampling with phase adjustment is used to cope with high skews, then data recovery accuracy is improved, but device complexity increases due to phase-locked loops and delay-locked loops
Solution Approach 1:
The patent replaces the mechanical/analog phase adjustment system (PLL, DLL, variable delay lines) with a digital system. Multiple fixed delay lines are implemented in digital logic, and a digital controller selects and adjusts the delay amount based on detected skew conditions, thereby reducing analog complexity while maintaining accuracy.
Solution Approach 2:
The patent implements dynamic skew compensation by making the delay line selection and delay amount adjustable based on detected transmission conditions. The system dynamically adapts to varying skews under changing transmission conditions (such as cable bending) by recalibrating the delay settings, rather than using fixed synchronous sampling.
2Productivity
If multiple sampling phases are used to reduce maximum system frequency, then productivity is improved, but device complexity increases due to additional sampling circuits
Solution Approach 1:
The patent combines multiple fixed delay lines into a single integrated delay compensation unit. Instead of implementing separate sampling circuits for each phase, the system uses one sampling circuit that can be dynamically adjusted to different delay settings, merging the functionality of multiple phases into a single adaptable structure.
Solution Approach 2:
The sampling circuit is designed to be multi-functional, capable of operating at different delay settings to handle various skew conditions. The same sampling circuit serves multiple purposes by adjusting its delay parameter, rather than requiring dedicated circuits for each sampling phase.
3Measurement precision
If synchronous super sampling with fixed sampling phase ratios is used, then measurement precision is improved, but adaptability worsens due to reliance on fixed ratios and analog filter loops
Solution Approach 1:
The patent transitions from fixed synchronous super sampling to dynamic asynchronous sampling. The sampling clock is no longer locked to a fixed phase ratio with the data clock, but instead runs asynchronously and allows dynamic adjustment of the sampling phase and delay amount based on detected skew conditions, enabling adaptation to varying transmission conditions.
Solution Approach 2:
The system changes the sampling parameters dynamically by adjusting the delay amount and sampling phase based on detected transmission conditions. Instead of maintaining fixed sampling phase ratios, the system modifies these parameters in response to varying skews caused by factors such as cable bending or transmission line variations.
Data Source
AI summary
In order to provide an interface circuit (100; 100′) as well as a method for receiving and/or for decoding, in particular for recovering, data signals (D; R, G, B), in particular high speed data signals, for example high speed sequential digital data signals, wherein at least one sampling clock signal (SC), in particular at least one multi-phase sampling clock signal (PC[n-1:0]) with n different phases, and/or the data signals (D; R, G, B) are delayed, and wherein it is possible to optimize the components, in particular the analog components, for a fixed operating frequency, it is proposed that the sampling clock signal (SC), in particular the multi-phase sampling clock signal (PC[n-1:0]), is asynchronous—to at least one interface clock signal (IC), by which the interface circuit (100; 100′), in particular the input of the interface circuit (100; 100′), can be provided with, and/or to the data signals (D; R, G, B).