Asynchronous Data Sampling Clock Phase Alignment at Low Frequency
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Solution Overview
Problem
Conventional asynchronous communication receivers are resource intensive due to high frequency clock rates and extensive post-sampling processing, making them difficult to implement on microcontrollers with limited bandwidth and system clock frequencies.
Innovation Solution
An asynchronous data capture device comprising an edge spread detector circuit, a clock generator, and a data sampling circuit that identifies a sampling point isolated from data transitions, generating a low frequency clock signal with a rising edge at that point, allowing sampling at a frequency corresponding to the data clock frequency, reducing the need for extensive oversampling and post-processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional sampling methods are used for asynchronous data capture, then device complexity is reduced, but measurement precision deteriorates due to inability to accurately identify sampling points in low frequency signals
Solution Approach 1:
The patent introduces a down-converter as an intermediary device that converts the high frequency asynchronous sampling clock to a lower frequency clock that matches the input signal frequency. This intermediary clock serves as a bridge between the high frequency sampling system and the low frequency signal, enabling accurate sampling point identification without requiring direct high frequency operation on the signal processing path.
Solution Approach 2:
The patent replaces direct high frequency electronic sampling with a frequency conversion approach using a down-converter. Instead of directly sampling the low frequency signal at high frequencies, the system converts the high frequency sampling clock down to the signal frequency, substituting a frequency conversion mechanism for direct mechanical/electronic sampling at the original frequency.
2Productivity
If high frequency sampling clocks are used, then sampling rate is improved, but measurement precision deteriorates due to period uncertainty in low frequency signals
Solution Approach 1:
The patent applies preliminary frequency conversion to counteract the period uncertainty problem. By down-converting the high frequency sampling clock to match the low signal frequency before sampling occurs, the system pre-establishes a reference clock with the same frequency characteristics as the signal, thereby eliminating period uncertainty and enabling precise sampling point identification.
Solution Approach 2:
The patent changes the frequency parameter of the sampling clock from high frequency to low frequency through the down-converter. This parameter transformation allows the sampling clock to synchronize with the low frequency input signal, resolving the mismatch between sampling rate requirements and signal frequency characteristics.
3Loss of information
If direct asynchronous sampling is performed, then device complexity is reduced, but loss of information increases due to inability to capture accurate signal characteristics
Solution Approach 1:
The down-converter acts as an intermediary that preserves signal characteristics by converting the sampling clock frequency to match the signal frequency. This intermediary frequency conversion process maintains the temporal relationships and characteristics of the low frequency signal while enabling high rate sampling, thereby preventing information loss without requiring complex direct sampling architectures.
Data Source
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AI summary
An asynchronous data capture device (300) comprises an edge spread detector circuit (310), a clock generator (320), and a data sampling circuit (330). The edge spread detector circuit uses a first clock frequency that is a multiple of a second clock frequency, identifies transitions in a data stream transmitted to the device (305) at the second clock frequency, and determines a sampling point (315) based on the identified transitions. The clock generator adjusts a phase offset based on the sampling point and generates a clock signal (325) having the second clock frequency and the adjusted phase offset. The data sampling circuit uses the second clock frequency and samples the data stream at the sampling point. In some implementations, the edge spread detector determines a sampling point that is isolated from the identified transitions, and the clock generator adjusts the phase offset to cause a rising edge at the sampling point.