Asynchronous SAR ADC Bit-Slice Control for Lower Power Conversion
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Solution Overview
Problem
Traditional successive approximation analog-to-digital converters (SAR ADCs) require a large number of clock cycles for n-bit conversion, leading to high power consumption due to the need for a complicated state-machine running at an oversampled clock.
Innovation Solution
An asynchronous SAR ADC architecture using dynamic logic controlled by asynchronous signals, with a chain of identical bit-slices activated one after the other, minimizing power consumption by avoiding clock-related switching losses and allowing self-timed operation, and a standby controller to place significant parts of the ADC in low power mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional SAR ADC uses a large number of clock cycles for n-bit conversion, then the conversion can be completed with a simple state-machine, but the power consumption increases due to the complicated state-machine running at an oversampled clock
Solution Approach 1:
The converter is divided into multiple identical bit-slices, each handling a specific bit position. This segmentation allows each slice to operate independently and asynchronously, eliminating the need for a complex centralized state-machine that coordinates all bits across multiple clock cycles. Each bit-slice processes its bit position in parallel, reducing overall complexity and power consumption.
Solution Approach 2:
The patent employs dynamic logic circuits within each bit-slice that can change state based on the comparison result. The logic circuits are designed to be activated only when needed, allowing the system to adapt its operation dynamically rather than following a rigid clocked sequence. This dynamic approach reduces switching activity and power consumption while maintaining conversion functionality.
2Speed
If a conventional SAR ADC runs at an oversampled clock to complete n-bit conversion in a reasonable time, then the conversion speed is improved, but the power consumption increases due to clock-related switching losses
Solution Approach 1:
Instead of using continuous periodic clocking, the patent implements periodic action only when necessary through asynchronous event-driven operation. Each bit-slice is activated periodically based on the completion of previous bit comparisons, rather than being continuously clocked. This eliminates unnecessary switching losses while maintaining conversion speed through efficient use of clock cycles.
Solution Approach 2:
The bit-slices are designed to self-activate and self-complete their operation without external clock intervention. Once a bit-slice completes its comparison and determines the bit value, it automatically triggers the next bit-slice to activate. This self-service mechanism eliminates the need for a central clock to synchronize all operations, reducing clock-related switching losses while maintaining conversion speed.
3Ease of manufacture
If identical bit-slices are used to reduce design complexity, then the manufacturing ease is improved, but the ability to handle variable conversion speeds and bit lengths requires additional control mechanisms
Solution Approach 1:
Each bit-slice is designed as a universal module that can handle any bit position in the conversion process. The identical structure of all bit-slices allows them to perform the same fundamental function of comparing and determining a bit value, regardless of position. This universality simplifies manufacturing and design while the flexible interconnection of these universal modules allows adaptation to different conversion speeds and bit lengths without requiring complex control mechanisms.
Data Source
AI summary
An asynchronous analog to digital convertor for converting an analog input signal into a digital output is presented. According to an embodiment, the analog to digital convertor comprises a clock input operable to receive an external clock signal having a clock period, a comparator operable to compare the analog input signal to a reference signal, a digital to analog converter operable to generate the reference signal corresponding to a state of a successive approximation register, and a control block connected to the comparator and to the digital to analog converter. The control block is operable to generate and receive a sequence of control signals according to a successive approximation algorithm, to perform a plurality of comparisons, and to update the state of the successive approximation register thereby generating the digital output.