Asynchronous SAR ADC Timing With Redundant Bits and Preemptive Decisions
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Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converters (ADCs) are limited in speed due to the settling time of digital-to-analog converters (DACs) and metastability issues in comparators, leading to inefficiencies in data conversion.
Innovation Solution
The implementation of asynchronous SAR ADCs with overlapping redundant bits in DAC code words, which generate an indication signal for each comparison step and use a timer to preempt decisions if the settling time exceeds a threshold, ensuring the difference between input and output voltages falls within an overlapping range, thereby reducing settling time and preventing metastability errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional SAR ADC is used to achieve high resolution, then conversion accuracy is improved, but conversion speed deteriorates due to DAC settling time limitations
Solution Approach 1:
The patent segments the conversion process into multiple phases with different resolution requirements. Early bits are converted with full resolution requirements, while later bits use reduced resolution thresholds. This segmentation allows the DAC to settle to coarser levels for later bits, reducing settling time while maintaining overall conversion accuracy.
Solution Approach 2:
The patent applies partial action by converting only the necessary number of bits to the required accuracy threshold. Instead of uniformly converting all bits to full precision, the system stops conversion when the accumulated error is within acceptable bounds, reducing the total conversion time while maintaining measurement precision.
2Measurement precision
If conventional SAR ADC is used to achieve high resolution, then conversion accuracy is improved, but conversion speed deteriorates due to comparator metastability
Solution Approach 1:
The patent dynamically adjusts the voltage threshold for bit conversion based on the current conversion state and accumulated error. Instead of using fixed thresholds, the system adapts the decision boundary in real-time, allowing faster comparator decisions while maintaining accuracy. This dynamic approach prevents metastability by ensuring comparisons are made at optimal voltage points.
Solution Approach 2:
The patent implements feedback by continuously monitoring the conversion progress and accumulated quantization error, then using this information to adjust subsequent conversion thresholds. The system feeds back the current state to the decision logic, enabling adaptive threshold selection that prevents comparator metastability while preserving conversion accuracy.
3Speed
If DAC settling time is reduced to improve speed, then conversion speed is improved, but conversion accuracy deteriorates due to insufficient settling
Solution Approach 1:
The patent applies partial action by accepting that later bits will have coarser resolution and larger quantization errors. Instead of requiring all bits to settle to full precision, the system converts only enough bits to achieve the target accuracy, allowing the DAC to settle to appropriate levels for each bit position rather than maximum precision for all bits.
Solution Approach 2:
The patent changes the resolution parameter dynamically during conversion. Early bits use high resolution requirements, while later bits use reduced resolution thresholds. This parameter change allows the DAC settling time to be reduced for later bits while maintaining overall conversion accuracy through adaptive threshold adjustment.
4Reliability
If conversion threshold is reduced to prevent metastability, then reliability is improved, but conversion speed deteriorates due to additional comparison steps
Solution Approach 1:
The patent dynamically adjusts the conversion threshold based on the current bit position and accumulated error, rather than using a fixed low threshold for all bits. This dynamic thresholding maintains reliability by ensuring adequate noise margins while avoiding unnecessary comparison steps that would reduce speed.
Solution Approach 2:
The patent changes the decision threshold parameter adaptively during conversion. Instead of uniformly applying a conservative low threshold, the system adjusts thresholds based on the current conversion state, maintaining reliability where needed while enabling faster conversion when the signal margin is sufficient.
Data Source
AI summary
An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.