Asynchronous Scan Capture for Multi-Clock Domain Timing
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Solution Overview
Problem
In system-on-chip (SOC) designs with multi-clock domains, the clock imbalance during scan capture operations poses timing issues, making it difficult to synchronize clock trees across different domains, especially when using a single scan clock from an external tester.
Innovation Solution
The system employs a shift register, a one-hot n-to-2n decoder, integrated clock gating cells (ICGs), and multiplexers to process select data and generate one-hot codes, enabling only one clock domain to be active during scan capture operations, thus avoiding timing issues by asynchronously managing clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single scan clock is used to clock all multi-clock domains during scan capture operation, then the scan capture operation can be performed, but timing issues appear due to clock imbalance across the multi-clock domains
Solution Approach 1:
The patent divides the multi-clock domains into separate groups, with each group having its own dedicated scan clock. This segmentation allows each clock domain to be clocked independently with appropriate timing, avoiding the timing issues that would arise from using a single scan clock for all domains. The scan chain is also segmented to interface with specific clock domains rather than all domains simultaneously.
Solution Approach 2:
The patent introduces scan domain interface logic as an intermediary between the scan chain and the multi-clock domains. This interface logic selectively couples the scan chain to specific clock domains based on control signals, enabling controlled access to different clock domains during scan operations. This intermediary manages the clocking relationships and prevents timing conflicts.
2Reliability
If scan chains of different clock domains are isolated or lockup latches are used during scan-shift operation, then clock imbalance may be solved, but during scan-capture operation many data paths still violate timing across imbalanced clock trees
Solution Approach 1:
The patent creates a universal scan interface structure that can handle multiple clock domains through a standardized mechanism. The scan domain interface logic and multiplexer-based selection provide a multi-functional approach that works for both scan-shift and scan-capture operations across different clock domains, eliminating the need for domain-specific isolation techniques.
Solution Approach 2:
The patent employs dynamic clock domain selection during scan operations. The scan domain interface logic dynamically couples or decouples the scan chain from different clock domains based on the operation phase (scan-shift vs. scan-capture) and the specific clock domain being accessed. This dynamic control allows timing-appropriate clocking without requiring static isolation structures.
3Reliability
If additional shift registers and hold buffers are added to solve timing issues, then timing reliability improves, but the area of SOC devices increases
Solution Approach 1:
The patent enables each clock domain to serve its own timing requirements through dedicated scan clocks and interface logic. Rather than adding extensive buffering infrastructure, the system allows each domain to self-manage its clocking independently, with the interface logic providing selective coupling. This reduces the need for additional area-consuming buffers while maintaining timing integrity.
Data Source
AI summary
A system, circuit, and device for asynchronously scan capturing multi-clock domains. A system includes a shift register configured to process select data for selecting a clock domain at a time in response to a scan capture pulse and a one-hot n-to-2n decoder connected to the shift register and configured to generate one-hot code based on the select data. The system also includes integrated clock gating cells connected to the one-hot n-to-2n decoder, where the scan capture pulse is applied to each one of the integrated clock gating cells, and where only one of the integrated clock gating cells associated with the clock domain is enabled when the one-hot code is processed by the integrated clock gating cells. Further, the system includes multiplexers connected to the integrated clock gating cells, where the multiplexers are configured to forward the scan capture pulse to the clock domain.