Asynchronous Sequential Writing Circuit for Two-to-Four-Phase Handoff
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Solution Overview
Problem
Asynchronous circuits that transition from a two-phase communication model to a four-phase protocol during synthesis often malfunction, leading to operational blocks due to the simplification of channel connections.
Innovation Solution
The implementation of a circuit design that includes an input channel, divergence and convergence operators, a main sequencer with control channels, switches, and memory circuits to manage request and acknowledgment signals, ensuring proper state transitions without altering the input channel's state, thereby facilitating smooth protocol phase execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the circuit is implemented according to the two-phase protocol, then the circuit speed and energy efficiency are improved, but the circuit malfunctions and blocks when synthesized into four phases
Solution Approach 1:
The patent introduces intermediate channels between the input and output channels to mediate the protocol transition. These intermediate channels act as buffers that decouple the two-phase input channel from the four-phase output channel, allowing the circuit to maintain high-speed two-phase operation while correctly implementing four-phase protocol requirements at the output.
Solution Approach 2:
The patent segments the single input-output channel connection into multiple intermediate channels. By dividing the communication path into segments (input channel → intermediate channels → output channel), the system can apply different protocol phases to different segments, enabling the input to operate in two-phase mode while the output operates in four-phase mode.
2Device complexity
If the channel connection is simplified by reducing to a single wire in two-phase mode, then the device complexity is reduced, but the circuit blocks when simulated in four phases after synthesis
Solution Approach 1:
The patent resolves the contradiction by transitioning from a one-dimensional simplified wire connection to a multi-dimensional channel structure. Instead of using a single wire for both phases, the system introduces multiple intermediate channels with distinct request and acknowledgment paths, adding dimensional complexity that enables proper four-phase operation while maintaining simplicity in the two-phase operational mode.
3Device complexity
If the request signal is transmitted directly through intermediate channels, then the device complexity is reduced, but the protocol phases cannot be correctly executed in four-phase mode
Solution Approach 1:
The patent applies preliminary action by introducing control channels that prepare and manage the state of intermediate channels before data transmission. The control channels pre-establish the necessary conditions for protocol phase execution, ensuring that request and acknowledgment signals are properly handled in four-phase mode without requiring complex additional control mechanisms during operation.
Data Source
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AI summary
The circuit has a divergence operator (20) connecting an input channel to intermediate channels (O1, O2), and a convergence operator (22) gathering the intermediate channels in an output channel (Z). A main sequencer (SEQ) includes sequentially-activated control channels (S1, S2). A memory circuit (MEM) is connected to an associated control channel, to transmit a request signal from an associated intermediate channel to the output channel, and to modify an output state of the associated intermediate channel, by the main sequencer, without requiring any state change of the input channel.