Asynchronous Serial Communication Without Clock-Line Interference

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Solution Overview

Problem

Conventional synchronous master-slave serial communication systems are prone to system instability and data errors due to interference and long-range transmission issues affecting the clock signal.

Innovation Solution

An asynchronous master-slave serial communication system is introduced, where a master control module generates a data package with a check code and master clock signal, and a slave control module decodes it using a slave clock signal, eliminating the need for a clock transmission line and reducing interference-related errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If synchronous master-slave serial communication is used with clock signal transmission, then data transmission timing is synchronized, but clock signal interference and degradation occur during long-range transmission

Engineering Contradiction:
Improvedata transmission accuracyVSAvoidclock signal interference
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts and removes the clock signal transmission line from the communication system. The master control module transmits only data packages containing start bits, data bits, and stop bits, while the slave control module generates its own clock signal for decoding. This eliminates the clock signal interference and degradation issues during long-range transmission while maintaining synchronized data transmission through the structured data package format.

Inventive Principle:
Principle #2Taking out (Extraction)

2Productivity

If clock signal is transmitted over long distance, then synchronous communication is achieved, but signal decay and interference increase

Engineering Contradiction:
Improvecommunication efficiencyVSAvoidclock signal degradation
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The clock signal transmission function is extracted and removed from the communication system. The slave control module generates its own clock signal locally, eliminating energy loss and signal degradation during long-distance transmission. Data transmission efficiency is maintained through the structured data package format with clear start and stop bits that enable accurate synchronization without requiring physical clock signal transmission.

Inventive Principle:
Principle #2Taking out (Extraction)

3Object-affected harmful factors

If asynchronous communication without clock transmission is used, then interference is reduced, but data synchronization becomes more challenging

Engineering Contradiction:
Improvesignal interferenceVSAvoiddata package structure
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The master control module performs preliminary actions by embedding synchronization information directly into the data package structure before transmission. Each data package includes a start bit that signals the beginning of data transmission, data bits that carry the actual information, and stop bits that mark the end. This preliminary structuring enables the slave control module to synchronize data reception using its own locally generated clock signal, eliminating the need for separate clock transmission while maintaining accurate synchronization.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8861553B2Asynchronous master-slave serial communication system, data transmission method, and control module using the same thereof
Publication Date: 2014.10.14 IND TECH RES INST
  • US8861553B2 patent drawing
  • US8861553B2 patent drawing
  • US8861553B2 patent drawing

AI summary

An asynchronous master-slave serial communication system, a data transmission method, and a control module using the same are disclosed. The asynchronous master-slave serial communication system comprises a master control module and a slave control module. The master control module generates a check code according to an address information and a data information, and generates a data package according to the address information, the data information, the check code and the master clock signal. The slave control module generates a decoding data according to the data package and a slave clock signal, and generates the address information, the data information and the check code according to the decoding data.