Asynchronous Signal Latch Circuit for Switching Noise Suppression
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Solution Overview
Problem
Switching noise in circuits, particularly in mixed signal systems, affects analog and digital circuits due to synchronized clock signals, leading to performance degradation and increased power consumption when synchronizing clock signals to reduce noise.
Innovation Solution
Implementing a method where signal propagation is delayed outside a defined time window between changes in asynchronous clock signals, allowing a third signal to propagate only after a delayed version of the first clock signal changes, using a digital logic circuit with a latch and Schmitt trigger to manage noise by holding the signal until the second clock signal change.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If clock signals are synchronized between data clock and internal clock to reduce noise effects on analog data sampling, then noise reduction is achieved, but circuit performance degrades due to hard delay of at least half cycle or one cycle
Solution Approach 1:
The patent applies preliminary action by defining a forbidden time window in advance, before the actual sampling operation, during which signal propagation is prevented. This window is established based on predicted clock transitions, allowing the circuit to proactively avoid noise periods without requiring reactive synchronization delays. The latch is configured to block propagation during this pre-defined window, enabling noise avoidance without performance penalty.
2Object-affected harmful factors
If clock signals are synchronized to reduce switching noise, then noise effects on analog data sampling are reduced, but additional circuitry consumes die area and power
Solution Approach 1:
The patent extracts the noise management function from complex clock synchronization circuitry and implements it through a simple latch-based propagation control mechanism. By removing the need for additional synchronization circuits, counters, and control logic, the solution isolates the essential noise avoidance function into minimal circuitry that uses existing latch structures already present in the data path.
3Speed
If signal propagation is allowed continuously, then circuit speed is maintained, but noise is generated during clock signal transitions
Solution Approach 1:
The patent implements periodic action by introducing a time-windowed propagation control mechanism that periodically enables and disables signal propagation based on clock signal phases. The latch is controlled to allow propagation only during safe time windows between predicted clock transitions, creating a rhythmic pattern of enable/disable states that aligns with the clock periodicity, thereby preventing noise generation while maintaining overall signal flow.
Data Source
AI summary
Noise may be reduced by delaying signal propagation outside of a time window when a change in another signal is expected. A time window may be defined between the change of the first clock signal and the change of the second clock signal during which a third signal, such as a data signal, does not propagate through the circuit. When a change occurs in a third signal after the first clock signal change while the first clock signal is at a different level than a second clock signal, propagation of the third signal change may be delayed until a change in the second clock signal is received. Delayed propagation may be achieved through a latch and hold circuit with no metastability.