Asynchronous Signal Delay Circuit With Split Timing Control
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Solution Overview
Problem
Existing delay apparatuses for asynchronous input signals rely on capacitors or multistage logic circuits, which can lead to increased size and complexity when longer delay times are required, and may not accurately reproduce the detection delay time.
Innovation Solution
The proposed delay apparatus includes a synchronous delay unit and an asynchronous delay unit, utilizing a counter and capacitors to accurately determine and implement delay times, allowing for separate detection of synchronous and asynchronous delay timings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If a capacitor or multistage logic circuit is used to clock a delay time, then the delay time can be extended, but the apparatus size increases
Solution Approach 1:
The delay apparatus is divided into two independent functional units: a synchronous delay unit that handles synchronous delay timing using a counter, and an asynchronous delay unit that handles asynchronous delay timing using a capacitor. By segmenting the delay function into these two units, each unit can be optimized independently, preventing the need for a large multistage logic circuit while achieving the required delay time.
2Duration of action of moving object
If a capacitor or multistage logic circuit is used to clock a delay time, then the delay time can be extended, but the device complexity increases
Solution Approach 1:
The delay apparatus is divided into two independent functional units: a synchronous delay unit that handles synchronous delay timing using a counter, and an asynchronous delay unit that handles asynchronous delay timing using a capacitor. By segmenting the delay function into these two units, each unit can be optimized independently, preventing the need for a large multistage logic circuit while achieving the required delay time.
Solution Approach 2:
A delay time acquisition unit is introduced as an intermediary component that acquires the asynchronous delay timing and provides it to the asynchronous delay unit. This mediator enables the asynchronous delay unit to accurately reproduce the detection delay time without requiring complex circuitry, as the intermediary handles the timing acquisition and conversion.
3Measurement precision
If existing delay apparatus structures are used, then the implementation is simple, but the detection delay time cannot be accurately reproduced
Solution Approach 1:
A delay time acquisition unit is introduced as an intermediary component that acquires the asynchronous delay timing and provides it to the asynchronous delay unit. This mediator enables the asynchronous delay unit to accurately reproduce the detection delay time without requiring complex circuitry, as the intermediary handles the timing acquisition and conversion.
Solution Approach 2:
The invention changes the operational parameters of the delay units by using a counter for synchronous delay timing and a capacitor for asynchronous delay timing. This parameter change allows the system to accurately reproduce the detection delay time by matching the timing characteristics of the original signal change, rather than using a fixed multistage logic circuit approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate reproduction of the detection delay time and generation of a delayed signal with the desired delay time, while preventing an increase in apparatus size due to longer delay times.
Implementation Method 1
a capacitor or a multistage logic circuit has been hitherto used to clock a delay time from a change timing of the input signal to a change in an output signal
Data Source
AI summary
Provided is a delay apparatus which outputs a delayed signal obtained by delaying an asynchronous input signal, the delay apparatus comprising: a synchronous delay unit which determines, in response to detection of a change in the asynchronous input signal at a detection timing synchronous with a clock signal, a synchronous delay timing later than the detection timing by a reference delay time according to the clock signal; and an asynchronous delay unit which changes the delayed signal at an asynchronous delay timing obtained by delaying the synchronous delay timing by an adjustment time obtained by subtracting a detection delay time from a change timing of the asynchronous input signal to the detection timing from a set time according to the clock signal.