Asynchronous Signal Synchronization in Parallel Data Processors
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Solution Overview
Problem
In data processing systems with asynchronous logic, synchronizing signals across different clock domains can lead to false errors when multiple processors operate in parallel, particularly due to slight timing differences in clock signals, which is problematic in safety-critical applications.
Innovation Solution
A data processing apparatus with synchronizers to synchronize signals from one clock domain to another, allowing for the export and re-import of synchronized signals across multiple processors, using combining logic like AND or OR gates to ensure synchronized input to further logic, thereby preventing false error generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processors operate in parallel with asynchronous logic, then processing capability is improved, but false errors are generated due to timing differences in clock signals
Solution Approach 1:
A synchronizer circuit is introduced as an intermediary component between the first clock domain (clk1) and second clock domain (clk2). The synchronizer receives signals from the first clock domain and produces synchronized signals for the second clock domain, acting as a mediator that eliminates timing conflicts. This intermediary structure allows parallel processors to operate independently in their own clock domains while ensuring coherent signal transmission across domain boundaries, preventing false errors without reducing processing capability.
2Reliability
If synchronizers are added to synchronize signals between clock domains, then false errors are prevented, but device complexity increases
Solution Approach 1:
The synchronizer circuit is designed as a segmented, modular structure with distinct functional blocks: a first register stage for initial synchronization, a second register stage for further stabilization, and combining logic for signal integration. This segmentation allows the synchronizer to be implemented as a compact, standardized component that can be easily integrated into parallel processor systems without significantly increasing overall system complexity.
Solution Approach 2:
The synchronizer utilizes parameter changes in the signal domain by transitioning signals from one clock domain's timing parameters to another clock domain's timing parameters. By changing the temporal parameters of the signal (its clock reference) rather than altering the fundamental signal structure, the synchronizer achieves domain conversion with minimal added complexity.
3Stability of the object's composition
If clock signals are synchronized across processors, then timing consistency is improved, but power consumption increases due to additional buffers
Solution Approach 1:
The invention extracts the synchronization function from the traditional clock distribution network with its power-consuming buffers. Instead of using buffered clock trees to synchronize signals, the synchronizer uses a lightweight register-based approach that operates directly on the signal edges. This extraction of the essential synchronization function eliminates the need for power-intensive buffering while maintaining timing consistency across parallel processors.
Data Source
AI summary
A data processing apparatus comprising a plurality of data processors, each data processor comprising: first logic operable in a first clock domain and further logic operable in a second clock domain, said first and second clock domains being asynchronous with each other; a synchronizer operable to synchronize a signal processed by said first logic to produce a signal synchronized to said second clock domain; a synchronized signal output operable to export from said data processor said synchronized signal output from said synchronizer; and a signal input operable to import a signal to said data processor, said data processor being operable to route said imported signal to said further logic; wherein said plurality of data processors are arranged to operate in parallel with each other and said data processing apparatus further comprises: combining logic arranged to receive said exported synchronized signals from each of said plurality of data processors and to combine said exported synchronized signals to produce a resultant signal, said resultant signal being routed to each of said signal inputs of said plurality of data processors.