Clock-Asynchronous SRAM Read Control Across Different Frequencies
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Solution Overview
Problem
Conventional dual-ported SRAMs for data transmission in electronic devices are characterized by large area and high cost, despite allowing operations at different frequencies.
Innovation Solution
Implementing a single-ported SRAM with a clock asynchronous processor that prioritizes read operations over write operations, enabling data transmission at different frequencies while reducing circuit area and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual-ported SRAM is used for data transmission between functional circuits operating at different clock frequencies, then read and write operations can be performed at different frequencies, but the circuit area becomes large and cost increases
Solution Approach 1:
The patent divides the data transmission function into two separate single-ported SRAMs, each dedicated to either read or write operations. This segmentation allows each SRAM to be optimized for its specific function while operating at different clock frequencies, achieving the versatility of dual-ported SRAM without the area penalty of implementing a true dual-ported structure.
2Adaptability or versatility
If dual-ported SRAM is used for data transmission between functional circuits operating at different clock frequencies, then read and write operations can be performed at different frequencies, but cost increases
Solution Approach 1:
The patent divides the data transmission function into two separate single-ported SRAMs, each dedicated to either read or write operations. This segmentation allows each SRAM to be optimized for its specific function while operating at different clock frequencies, achieving the versatility of dual-ported SRAM without the area penalty of implementing a true dual-ported structure.
3Area of stationary object
If a single-ported SRAM is used instead of dual-ported SRAM, then circuit area is reduced and cost is lowered, but the ability to perform simultaneous read and write operations at different frequencies is lost
Solution Approach 1:
The patent divides the data transmission function into two separate single-ported SRAMs, each dedicated to either read or write operations. This segmentation allows each SRAM to be optimized for its specific function while operating at different clock frequencies, achieving the versatility of dual-ported SRAM without the area penalty of implementing a true dual-ported structure.
Solution Approach 2:
Each single-ported SRAM is designed to handle its dedicated operation (read or write) across multiple clock frequency domains. The read SRAM can be accessed by the first functional circuit at its clock frequency while the write SRAM handles writes from the second functional circuit at its clock frequency, providing multi-frequency adaptability within the constraints of single-ported memory structures.
Data Source
AI summary
An electronic device includes a first functional circuit, a second functional circuit, a memory, and a clock asynchronous processor. The first functional circuit operates at a first clock and generates a read command. The second functional circuit operates at a second clock. The memory is coupled to the first functional circuit and the second functional circuit. The clock asynchronous processor is coupled to the first functional circuit and the memory and configured to check, according to the first clock and the second clock, whether the read command exists. When the read command exists, the clock asynchronous processor provides the read command to the memory.