Asynchronous Data Transfer Circuit for Non-Continuous Slave Clocks
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Solution Overview
Problem
Data transfer between master and slave devices with asynchronous clock signals is hindered by clock domain crossing issues, especially when the slave device uses a non-continuous clock signal, leading to data loss or errors, and existing solutions like FIFO buffers increase the complexity and size of the slave device.
Innovation Solution
A slave device with a clock detection circuit and datapath selector that generates a sync signal based on the presence of the slave clock signal, allowing seamless data transfer to the master device, independent of the slave clock signal's availability, using a command decoder, reset synchronizer, clock detection circuit, register bank, temporary storage register, and response generator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FIFO buffers are used to transfer data between master and slave devices, then data transfer reliability is improved, but device complexity and size increase
Solution Approach 1:
The patent extracts the clock synchronization function from the data path by using a dedicated clock detection circuit that operates independently. The sync signal generation is separated from the main data transfer logic, allowing the slave device to handle asynchronous clocks without requiring complex FIFO buffers, thus reducing overall device complexity while maintaining reliability
Solution Approach 2:
The patent introduces a sync signal as an intermediary between the slave clock domain and the data transfer operation. This sync signal acts as a mediator that coordinates data latching with clock availability, enabling reliable asynchronous data transfer without the need for large FIFO buffers, thereby reducing device complexity
2Reliability
If the data transfer cycle is extended to wait for slave clock signal availability, then data transfer reliability is improved, but productivity decreases
Solution Approach 1:
The patent uses a clock detection circuit that continuously monitors slave clock signal availability and generates the sync signal in advance of data transfer operations. This preliminary detection allows the master device to know when data can be transferred without extending the transfer cycle, maintaining high productivity while ensuring reliability
Solution Approach 2:
The sync signal provides continuous feedback about clock availability to the data transfer logic. This feedback mechanism allows the system to adapt to clock variations dynamically without stalling the data transfer, thus maintaining high productivity while ensuring reliable data latching when clocks are available
3Reliability
If clock synchronization techniques are used to resolve CDC issues, then data transfer reliability is improved, but the solution fails when slave clock signal is non-continuous
Solution Approach 1:
The patent implements a dynamic sync signal generation mechanism that adapts to the presence or absence of the slave clock signal. The clock detection circuit dynamically generates the sync signal based on real-time clock availability, allowing the system to handle both continuous and non-continuous clock scenarios, thereby improving adaptability while maintaining reliability
Data Source
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AI summary
A circuit for asynchronous data transfer includes a slave device having an asynchronous slave clock for transferring data to a master device having a master clock. The slave clock is a non-continuous clock signal. The slave device includes a clock detection circuit, a register bank, a temporary storage register, and a datapath selector. The slave device receives a data transfer command from the master device. The clock detection circuit detects a presence of the slave clock signal and generates a sync signal. To transfer the data to the master device, the datapath selector selects one of the temporary storage register and the register bank based on the sync signal. The slave device ensures seamless data transfer to the master device regardless of the presence or absence of the slave clock signal.