Asynchronous Data Transfer Circuit for Non-Continuous Slave Clocks
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Solution Overview
Problem
Data transfer between master and slave devices with asynchronous clock signals is hindered by clock domain crossing issues, especially when the slave device uses a non-continuous clock signal, leading to data loss or errors, and existing solutions like FIFO buffers increase the complexity and size of the slave device.
Innovation Solution
A slave device equipped with a clock detection circuit, a register bank, a temporary storage register, and a datapath selector that generates a sync signal to seamlessly transfer data to a master device, regardless of the slave clock signal's availability, by selecting between the register bank and temporary storage register based on the sync signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FIFO buffers are used to transfer data between master and slave devices, then data transfer reliability is improved, but device complexity and size increase
Solution Approach 1:
A dedicated clock detection circuit serves as an intermediary component that monitors the slave clock signal and generates a detect signal to coordinate data transfer timing between the master and slave devices, eliminating the need for complex FIFO buffers while ensuring reliable asynchronous data transfer
2Reliability
If the data transfer cycle is extended to wait for slave clock signal availability, then data transfer accuracy is improved, but productivity deteriorates
Solution Approach 1:
The clock detection circuit performs preliminary detection of the slave clock signal and generates the detect signal in advance, allowing the master device to precisely time its data transfer operations without extending the overall transfer cycle or waiting passively for clock availability
3Reliability
If clock synchronization techniques are used to resolve CDC issues, then data transfer reliability is improved, but they fail when slave clock signal is non-continuous
Solution Approach 1:
The clock detection circuit autonomously monitors the slave clock signal and self-adjusts the detect signal generation to match the actual clock availability, enabling the system to handle non-continuous clock signals without requiring complex synchronization protocols or extending transfer cycles
Data Source
AI summary
A circuit for asynchronous data transfer includes a slave device having an asynchronous slave clock for transferring data to a master device having a master clock. The slave clock is a non-continuous clock signal. The slave device includes a clock detection circuit, a register bank, a temporary storage register, and a datapath selector. The slave device receives a data transfer command from the master device. The clock detection circuit detects a presence of the slave clock signal and generates a sync signal. To transfer the data to the master device, the datapath selector selects one of the temporary storage register and the register bank based on the sync signal. The slave device ensures seamless data transfer to the master device regardless of the presence or absence of the slave clock signal.