Asynchronous Write Circuit Sequencing for Handshake Transition
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Solution Overview
Problem
Asynchronous circuits transitioning from a two-phase handshake protocol to a four-phase handshake protocol during synthesis often result in circuit malfunctions due to the simplification of channel connections, leading to blocking issues during sequential write operations.
Innovation Solution
The implementation of a divergent operator, convergence operator, main sequencer, and memory circuits within the asynchronous circuit, utilizing Muller C-elements and AND gates to manage request and acknowledgement signals, ensuring proper state transitions without requiring changes in the input channel's state, thereby facilitating smooth transition from two-phase to four-phase handshake protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a two-phase handshake protocol is used to describe and simulate circuit behavior, then the circuit speed and energy efficiency are improved, but the circuit may malfunction when synthesized into a four-phase handshake protocol implementation
Solution Approach 1:
The patent introduces intermediate control signals and control circuits that act as mediators between the two-phase functional model and the four-phase physical implementation. These intermediaries translate and coordinate the protocol transitions, ensuring that the simplified two-phase behavior correctly maps to the more complex four-phase implementation without malfunction.
Solution Approach 2:
The patent applies preliminary action by performing functional simulation and verification in the two-phase protocol before synthesis. The circuit behavior is described and validated in the simpler two-phase model first, then systematically transformed into the four-phase implementation, ensuring correctness is established before physical realization.
2Device complexity
If channel connections are simplified in the two-phase model, then the device complexity is reduced, but blocking issues occur during sequential write operations in the four-phase implementation
Solution Approach 1:
The patent segments the channel connection into multiple controlled stages with intermediate control signals. Instead of a single simplified connection, the channel is divided into segments with explicit control points that manage sequential write operations, preventing blocking while maintaining manageable complexity through modular control.
Solution Approach 2:
The patent introduces dynamic control signals that adaptively manage channel connections based on operational phase. The control circuits dynamically enable or disable specific connection paths during sequential writes, allowing the system to smoothly handle operations that static simplified connections cannot manage.
Data Source
AI summary
The asynchronous circuit includes an input channel, a divergence operator connecting the input channel to a plurality of intermediate channels, a convergence operator gathering the intermediate channels into a single output channel, a main sequencer including a plurality of sequentially-activated control channels, each intermediate channel being associated to a control channel, and a switch arranged in a request path of one of the intermediate channels and connected to the last active control channel. The circuit further includes a memory circuit, arranged in each of the other intermediate channels, connected to the associated control channel and configured to transmit the request signal of the associated intermediate channel to the output channel and to modify an output state of the associated intermediate channel, by means of the main sequencer, without requiring any state change of the input channel.