Asynchronous Multi-Stage ADC for Reconfigurable Resolution
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face challenges in simultaneously achieving high sampling rates and high resolution, as they become complex and power-consuming, and cannot be easily reconfigured to adapt to different operating requirements.
Innovation Solution
A multi-stage ADC architecture that uses asynchronous circuits, lookup tables, and level computing circuits to generate and modify input signals and reference ranges across stages, allowing for adaptable bandwidth and resolution without the need for complex circuit elements like sample-and-hold circuits or clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-resolution ADC is designed to achieve high number of bits, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The ADC is divided into multiple stages, where each stage processes a portion of the conversion. The first stage performs a coarse conversion with fewer bits, and subsequent stages perform finer conversions. This segmentation reduces the complexity of each individual stage while achieving high overall resolution through cascaded processing.
Solution Approach 2:
The patent introduces a time dimension by using sequential multi-stage processing. Instead of achieving high resolution in a single simultaneous operation, the conversion is distributed across multiple time steps with intermediate processing, effectively trading time for reduced instantaneous complexity.
2Measurement precision
If a high-resolution ADC is designed to achieve high number of bits, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The power consumption is segmented across multiple stages, with each stage consuming power proportional to its resolution requirement. The first stage consumes less power for coarse conversion, and subsequent stages consume incremental power for finer resolution, resulting in lower total power consumption compared to a single high-resolution stage.
Solution Approach 2:
The conversion process is divided into periodic stages that can be activated sequentially. Not all stages need to operate at full power simultaneously, and the system can enter lower-power states between conversion cycles, reducing average power consumption while maintaining high resolution capability.
3Device complexity
If subranging multi-stage ADC is used to reduce comparison circuits, then device complexity is reduced, but the ADC cannot be reconfigured for different operating requirements
Solution Approach 1:
The ADC system is designed with dynamic reconfigurability, allowing the number of active stages and their resolution allocation to be adjusted based on application requirements. The system can dynamically switch between high-resolution/low-bandwidth mode and low-resolution/high-bandwidth mode by activating or deactivating specific stages, providing adaptability while maintaining reduced complexity.
4Device complexity
If subranging multi-stage ADC is used, then the required number of comparison circuits is reduced, but power consumption remains relatively high due to additional circuit elements
Solution Approach 1:
The patent extracts and eliminates unnecessary circuit elements from the traditional subranging architecture. By removing the sample-and-hold circuit, DAC, latch, amplifier, and processor configured for error correction, the design retains only the essential comparison circuits and registration logic, significantly reducing power consumption while maintaining the complexity-reduction benefit of multi-stage processing.
Data Source
AI summary
A multi-stage analog-to-digital converter (ADC) suitable for low power applications, such as glucose monitoring, may be required to digitize a slow-moving signal. As such, a multi-stage ADC must be versatile. Accordingly, the multi-stage ADC can be configured to operate at different bandwidths and resolutions through the use of ADC stages that can be enabled or disabled in an exchange between resolution and speed. Each ADC stage digitizes an input signal (e.g., a voltage or a current) using an analog comparison to access a lookup table for a digital signal that represents the input signal at a particular accuracy. Unlike other multi-stage approaches, the digitization is asynchronous (i.e., requires no clock) and can provide simplicity, speed, and low-power operation to the multi-stage ADC.