Asynchronous ADC Sampling With Dynamic References and Time Stamps
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Solution Overview
Problem
Conventional analog-to-digital converters (ADCs) face high power consumption due to the use of numerous devices and high-speed oversampling to achieve desired resolution, leading to inefficiencies in power management.
Innovation Solution
The proposed ADC configuration includes a comparison circuit with dynamic reference signals generated by DACs, a time-to-digital converter (TDC) for timestamp generation, and a timer that enables sampling after a predetermined period, allowing for reduced comparator count and dynamic adjustment of reference signals to optimize sampling efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional synchronous ADC employs a large number of comparators and high-speed oversampling to achieve desired resolution, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic reference signal adjustment where the reference voltage levels are not fixed but are dynamically modified based on the input signal characteristics. The reference signals are adjusted to track the input signal envelope, allowing the comparators to operate with reduced precision requirements during low-activity periods while maintaining measurement precision during signal transitions, thereby reducing overall power consumption
Solution Approach 2:
The patent employs periodic sampling enabled by a timer that activates the ADC only at predetermined intervals rather than continuous operation. This periodic activation reduces power consumption by keeping the comparators and reference circuitry in a low-power state between sampling events, while still achieving the desired measurement precision through strategic timing of the sampling operations
2Measurement precision
If conventional ADC uses high-speed oversampling to achieve desired resolution, then measurement precision is improved, but productivity decreases due to unnecessary sampling operations
Solution Approach 1:
The patent implements a feedback mechanism where the output of the comparators is monitored for changes, and the sampling operation is controlled based on detected transitions. The system uses the comparator output state to determine when sampling is necessary, avoiding redundant sampling operations when the signal is stable, thereby improving productivity while maintaining measurement precision through event-driven sampling
Solution Approach 2:
The conversion circuit automatically detects changes in the comparator output and triggers sampling operations only when necessary. The system self-regulates the sampling rate based on signal activity, eliminating the need for external control logic to manage oversampling, and thereby improving productivity by performing only necessary conversion operations
3Measurement precision
If level-crossing ADC determines time at which analog signal crosses quantized levels, then measurement precision is improved, but device complexity increases due to additional timing circuitry
Solution Approach 1:
The patent combines the timing function with the existing comparator and conversion circuit operations. The time-to-digital converter is integrated into the conversion circuit block, sharing resources with the comparator output logic. This merging approach enables level-crossing detection precision while reducing device complexity by eliminating separate timing circuitry and using existing digital logic to perform time measurement functions
Data Source
AI summary
A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. If the comparison result remains substantially the same for a predetermined interval, an ADC is enabled to generate a second comparison result at a sampling instant. A second time stamp that corresponds to the sampling instant is generated. The second comparison result and a second time stamp corresponding to the first comparison result are registered, and a second portion of the digital signal is generated from the second comparison result.