Asynchronous Arbiter Latch Array for Metastability-Resistant FSMs

The arbitration function is divided into multiple independent latch elements, each handling a separate communication channel. Each latch independently captures events from its channel without interfering with others, eliminating the metastability problem that occurs when multiple channels are merged into a single arbitration point. The segmented architecture allows simultaneous event capture across channels while maintaining signal integrity.

Latch elements serve as intermediary components between the parallel communication channels and the arbitration logic. These latches buffer and stabilize the event signals before they reach the arbitration stage, preventing direct conflict between simultaneous events. The intermediary latches convert asynchronous simultaneous events into synchronized, stable signals that can be safely arbitrated.

Multiple communication channels are merged into a single bus interface that connects to the finite state machine. The latch array consolidates events from multiple channels into unified data and validity vectors, allowing the FSM to process concurrent events through a single, simplified interface rather than requiring separate arbitration logic for each channel combination.

The latch array serves multiple functions simultaneously: it acts as an event buffer, a validity detector, a data register, and an arbitration element. This multi-functional design eliminates the need for separate dedicated circuits for each arbitration task, reducing overall circuit complexity while maintaining the ability to handle concurrent events efficiently.

The global clock signal is extracted and removed from the asynchronous circuit architecture. Instead of relying on a centralized clock distribution network, the circuit uses local handshake protocols between components. The latch array and arbitration logic operate asynchronously, triggering events based on local signal transitions rather than global clock edges, thereby eliminating clock-related power consumption and improving robustness.

Each circuit component performs its own synchronization and timing management through local handshake signals without requiring external clock control. The latch elements automatically capture events when their enable conditions are met, and the arbitration logic self-regulates based on the timing of incoming signals. This self-synchronizing behavior eliminates the need for power-hungry global clock distribution while maintaining coordinated operation.