Asynchronous ASIC Clocking With Phase-Shifted Domains for Noise Control
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Solution Overview
Problem
Synchronous digital logic devices face issues with clock drift and resonant circuit noise due to synchronized transistor state transitions, leading to increased power consumption and complexity, especially in modern devices with high transistor density.
Innovation Solution
The implementation of phase-shifted-clock domains, where registers are synchronized to phase-shifted-clocks derived from a common reference clock, allowing staggered transistor state changes and reducing noise and power peaks, while maintaining the benefits of synchronized clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous circuits use the same global clock for multiple blocks, then clock drift problems are avoided, but resonant circuit noise increases due to large numbers of transistors toggling at once
Solution Approach 1:
The patent divides the clock domain into multiple phase-shifted-clock domains, where each domain uses a clock signal with a different phase offset. This segmentation allows transistor toggling to be distributed across different time phases rather than occurring simultaneously, reducing resonant circuit noise while maintaining overall clock synchronization across the system.
2Speed
If clock frequency is increased to improve performance, then processing speed increases, but resonant circuit noise and unwanted effects are amplified
Solution Approach 1:
By segmenting the clock distribution into multiple phase-shifted domains, the patent enables higher clock frequencies to be used without proportionally increasing resonant noise. The phase distribution spreads out the simultaneous transistor switching events, allowing performance improvement while controlling the amplification of unwanted effects.
3Object-generated harmful factors
If multiple independent local clocks are used for different blocks, then resonant circuit noise is reduced, but clock drift occurs requiring inefficient rebuffering operations
Solution Approach 1:
The patent introduces phase-shifted clocks as an intermediary solution between independent local clocks and a single global clock. These phase-shifted clocks are derived from a common reference clock, ensuring synchronization without requiring inefficient rebuffering operations, while still distributing transistor toggling to reduce resonant noise.
4Ease of operation
If synchronous circuits use a single clock domain, then data transfer is simplified, but power consumption increases due to synchronized transistor state transitions
Solution Approach 1:
The patent segments the clock domain into multiple phase-shifted domains, which distributes power consumption across different time phases. This allows data transfer to remain efficient while reducing peak power consumption by preventing all transistors from switching states simultaneously.
Data Source
AI summary
An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.