Asynchronous ASIC Clocking With Phase-Shifted Domains
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Solution Overview
Problem
Synchronous digital logic devices face issues with clock drift and resonant circuit noise due to synchronized transistor state transitions, leading to increased power consumption and complexity, especially in modern devices with high transistor density.
Innovation Solution
Divide clock domains into phase-shifted-clock domains, where each domain operates at the same frequency as a reference clock but with a phase shift, allowing staggered transistor state changes to reduce noise and power peaks, and use phase-shifted-clocks generated from a common reference clock to synchronize blocks within these domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous circuits use the same global clock to synchronize multiple blocks, then clock drift problems are avoided, but resonant circuit noise increases due to large numbers of transistors toggling at once
Solution Approach 1:
The patent divides the clock domain into multiple phase-shifted-clock domains, where each domain uses a clock signal with the same frequency but different phase shifts. This segmentation allows transistor toggling to be distributed across different time phases, reducing simultaneous switching noise while maintaining synchronization across the entire system through the common reference clock.
2Productivity
If clock frequency is increased to improve processing speed, then productivity increases, but resonant circuit noise and power consumption are amplified
Solution Approach 1:
The patent employs periodic phase shifting of clock signals across different domains, where each phase-shifted-clock domain operates at the same high frequency but with staggered phases. This periodic distribution of transistor switching events reduces peak noise and power consumption while maintaining the high processing speed enabled by the elevated clock frequency.
3Object-generated harmful factors
If multiple independent local clocks are used for different blocks, then resonant circuit noise is reduced, but clock drift requires inefficient rebuffering operations
Solution Approach 1:
The patent introduces phase-shifted clocks derived from a common reference clock as an intermediary mechanism. This allows different blocks to have locally different clock phases (reducing noise) while maintaining global synchronization through the reference clock, eliminating the need for rebuffering operations that would be required with completely independent clocks.
Data Source
AI summary
An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.