Asynchronous Two-Wire to Single-Wire Bus Conversion via Speculative Read
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Solution Overview
Problem
Existing systems for converting two-wire buses to single-wire buses are primarily synchronous and do not efficiently support asynchronous communication between master and slave circuits, particularly in systems where a master circuit connected to a two-wire bus needs to communicate with slave circuits connected via a single-wire bus.
Innovation Solution
An asynchronous conversion method is introduced, where an interface circuit sends a speculative read command to the slave circuit before interpreting the data, allowing for efficient data transmission by using a start-of-transmission signal, read control signals, and error messages on the single-wire bus, and automatically detecting addressing modes to facilitate communication between I2C protocol-based master circuits and single-wire protocol-based slave circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If synchronous conversion method is used between two-wire bus and single-wire bus, then the conversion can be completed using clock signal phases, but the system cannot efficiently support asynchronous communication between master and slave circuits
Solution Approach 1:
The interface circuit sends a speculative read command to the slave circuit before the master circuit actually needs the data. This preliminary action prepares the data in advance, allowing the system to transition from synchronous to asynchronous operation while maintaining efficient data transmission without requiring complex buffering mechanisms
Solution Approach 2:
The interface circuit acts as an intermediary between the two-wire I2C bus and the single-wire bus. It translates protocols, manages timing differences, and handles the speculative read commands, enabling asynchronous communication without requiring complex changes to either the master or slave circuits
2Loss of time
If speculative read command is sent before interpreting data state, then response time is extended, but the interface circuit must manage additional control signals
Solution Approach 1:
The speculative read command is sent in advance before the master circuit has fully interpreted whether a read or write operation is needed. This preliminary action allows the slave circuit to prepare data beforehand, reducing the overall response time while the interface circuit manages the additional control signals through protocol translation
Solution Approach 2:
The interface circuit monitors the state of data bits from the master circuit and uses this feedback to determine whether to proceed with the speculative read command or to cancel it. This feedback mechanism allows the system to extend response times when beneficial while avoiding unnecessary complexity when the master circuit's intent is clear
3Reliability
If error detection is implemented through frame demodulation and comparison, then transmission reliability is improved, but the slave circuit processing complexity increases
Solution Approach 1:
The slave circuit performs self-service error detection by demodulating the frame it sends and comparing the demodulated frame with the original frame. This self-service approach improves transmission reliability without requiring additional error detection hardware or complex processing in the interface circuit or master circuit
Solution Approach 2:
The slave circuit uses feedback from the demodulated frame comparison to detect errors in transmitted data. When inconsistencies are found, the slave circuit can request retransmission or handle the error appropriately, improving reliability while keeping the processing complexity localized to the slave circuit's existing demodulation capabilities
Data Source
AI summary
A method of conversion by at least one interface circuit connected between a first bus including at least one data wire and one clock wire, and at least one second single-wire bus, of a transmission between a master circuit connected to the first bus and at least one slave circuit connected to the second bus, wherein a speculative read command is sent to the slave circuit before interpreting the state of a bit for controlling a reading or a writing, originating from the master circuit.