Asynchronous Cache Flush Engine for Multi-Socket Systems
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Solution Overview
Problem
Current cache flush mechanisms in multi-processor systems require significant processor resources and time, especially when flushing coherent and memory-side caches, and existing native instructions either operate on a single cache line at a time or are non-interruptible and lack granular control.
Innovation Solution
A cache flush engine (CFE) that coordinates asynchronous, on-demand cache flushes across coherent and memory-side caches, allowing for finer granular control and offloading cache flush operations from system processors, with an administrative and command interface for controlling cache flush operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache flush operations are performed using existing native instructions, then cache lines can be flushed from coherent and memory-side caches, but significant processor resources and processing time are required
Solution Approach 1:
The patent extracts the cache flush operation from the main processor execution path by introducing a separate cache flush engine (CFE) that handles flush operations independently. The CFE receives flush requests from processors and executes them separately, allowing the main processor to continue normal operations without being blocked by cache flush operations.
Solution Approach 2:
The patent implements preliminary action by having the CFE proactively manage cache flush operations based on persistence requirements and cache state. The engine can initiate flush operations before they are strictly needed by application code, and can batch multiple flush operations together to reduce overall processor overhead.
2Stability of the object's composition
If cache flush operations are performed synchronously, then processor can ensure cache consistency, but processing time is significantly increased
Solution Approach 1:
The patent implements dynamics by transitioning from synchronous cache flush operations to asynchronous operations. The CFE allows processors to issue flush requests and continue execution without waiting for completion. The system dynamically tracks the state of flush operations and ensures coherence is maintained through status bits and completion tracking mechanisms.
Solution Approach 2:
The CFE acts as an intermediary between the processor and the cache coherence mechanism. It receives flush requests from processors, manages the actual flush operations to memory-side caches and persistent memory, and provides status information back to processors. This intermediary role allows the main processor to remain unaware of the detailed flush timing and coherence management.
3Adaptability or versatility
If fine-grained control over cache flush operations is implemented, then selective flushing of specific cache lines is possible, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the cache flush operation into distinct controllable units. The CFE can operate on individual cache lines, groups of cache lines, or entire caches based on flush requests. This segmentation allows fine-grained control where specific cache lines can be selectively flushed while leaving others intact, providing adaptability without requiring complete redesign of the cache system.
Data Source
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AI summary
Disclosed embodiments relate to an asynchronous cache-flush engine to manage platform coherent and memory-side caches. In one example, a system includes multiple interconnected sockets each including a cache flush engine (CFE), a core, and an associated cache hierarchy including a plurality of caches, one of the CFEs designated as a master CFE in a master socket, the master CFE to: receive a request specifying an opcode and a range, the opcode calling for a cache flush, execute the request to cause writeback and, if indicated by the request, invalidation of modified cache lines in the master socket falling within the range, and communicate a request to any other, slave sockets in the system each having a slave CFE to cause writeback and, if indicated by the request, invalidation of modified cache lines in the slave socket falling within the range.