Asynchronous Cellular Logic Arrays Without Global Clock Distribution
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Solution Overview
Problem
Cellular logic arrays face challenges in data and clock distribution, leading to synchronization issues and inefficiencies in large-scale applications, particularly in field programmable gate arrays (FPGAs), where conventional devices struggle with proper setup times and power consumption.
Innovation Solution
The development of an extensible FPGA architecture utilizing asynchronous triggered cellular automata, where cells are triggered by pulses and perform operations selectively, eliminating the need for a global clock, and allowing for cascaded configurations that support turns, forks, and joins, enabling efficient data and trigger routing without synchronization constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a global clock is used in conventional FPGAs, then synchronization can be achieved, but data distribution problems and setup time constraints arise
Solution Approach 1:
The patent removes the global clock signal from the FPGA architecture, extracting the synchronization mechanism that causes data distribution problems. Instead of using a centralized clock, the system employs asynchronous triggering where each cell is triggered by pulses from neighboring cells, eliminating the need for complex global clock distribution networks while maintaining operational coordination
Solution Approach 2:
The patent introduces trigger pulses as intermediary signals that mediate between cells without requiring a global clock. These pulses travel locally between neighboring cells, serving as a decentralized synchronization mechanism that avoids the data distribution constraints of conventional clocked architectures
2Productivity
If the array size is increased for large-scale applications, then processing capability improves, but clock distribution and setup time problems worsen
Solution Approach 1:
The patent segments the FPGA into independent cellular units that operate asynchronously. Each cell can be triggered and processed independently without waiting for global clock synchronization, allowing large arrays to scale without increasing setup time constraints. The segmentation enables parallel processing across all cells simultaneously
3Reliability
If conventional clocked logic is used, then synchronous operation is achieved, but power consumption increases
Solution Approach 1:
The patent replaces continuous clocking with periodic pulse-triggered action. Cells remain idle until triggered by a pulse, at which point they perform their logic operation and then return to idle state. This periodic activation pattern significantly reduces power consumption compared to continuous clocked operation, while still achieving coordinated synchronous-like operation through the trigger pulse propagation
Data Source
AI summary
An apparatus and method controlling cellular automata containing a plurality of cascaded circuit cells having logic units. The cells are interleaved in groups toward supporting multiple directions, for example quad cells in which each cells of the quad is directed in a different directions separated by a fixed angle, such as 90 degrees (i.e., north, east, south, and west). These cells are triggered asynchronously as each cell is stabilized in preparation for receiving the trigger. The cells process data selectively based on the configuration of the cell and in response to receipt of data and trigger (or combined data and trigger) conditions from neighboring cells. The array can be utilized within a wide range of digital logic. As there is no need for distributing a global clock across the array of cells, the size of the array can be extended to any desired dimension.