Asynchronous Circuit Conversion for Synchronous Inputs and Outputs
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Solution Overview
Problem
Existing methods struggle to convert synchronous circuit designs with asynchronous inputs into fully asynchronous designs, particularly in handling inputs, outputs, and event signals, as they rely on clock signals for synchronization, which is not applicable in asynchronous circuits.
Innovation Solution
The method converts synchronous circuit logic to asynchronous logic by generating tokens upon observing changes in asynchronous inputs and outputs, allowing asynchronous inputs to operate without a clock and outputs to provide updated data as soon as received, using edge detectors and special output converters to maintain compatibility with synchronous behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If synchronous circuit logic is converted to asynchronous logic, then the circuit can operate more efficiently without clock signals, but handling asynchronous inputs and outputs becomes complex
Solution Approach 1:
The patent introduces special output converters as intermediary components that bridge synchronous circuit logic and asynchronous inputs/outputs. These converters translate between synchronous behavior and asynchronous signaling, handling the complexity of event-driven interfaces while allowing the core circuit to operate efficiently in asynchronous mode.
Solution Approach 2:
The patent implements feedback mechanisms where asynchronous inputs generate tokens upon state changes, and output converters provide feedback signals to coordinate data flow. This feedback system manages the complexity of asynchronous I/O by creating structured communication protocols between circuit components.
2Reliability
If clock signals are used for synchronization, then circuit operation is coordinated, but power consumption increases and speed is limited by the slowest element
Solution Approach 1:
The patent extracts and removes clock signals from the asynchronous circuit implementation. By eliminating the global clock infrastructure, the circuit avoids the power consumption associated with clock distribution while maintaining coordination through event-driven token passing between components.
Solution Approach 2:
The patent implements dynamic operation where circuit elements operate at different speeds based on their individual requirements. Each element proceeds when ready, triggered by events rather than a rigid clock cycle, allowing faster elements to complete operations without waiting for slower ones while consuming power only when active.
3Ease of manufacture
If synchronous circuit design is used, then design and simulation are straightforward, but the circuit is limited by clock management and skew issues
Solution Approach 1:
The patent uses output converters as intermediary components that preserve synchronous-like behavior at internal interfaces while allowing asynchronous operation externally. These converters maintain design simplicity by providing familiar synchronous interfaces to designers while enabling asynchronous implementation benefits.
4Productivity
If asynchronous circuits are used, then power consumption is reduced and speed is improved, but handling various inputs, outputs, and event signals becomes challenging
Solution Approach 1:
The patent implements structured feedback mechanisms where event signals trigger token generation and propagation through the circuit. Output converters use feedback to coordinate when data is ready for output, providing clear signaling protocols that simplify the handling of asynchronous I/O while maintaining high-speed operation.
Solution Approach 2:
The patent introduces output converters as intermediary components that simplify asynchronous I/O handling by providing standardized interfaces. These converters manage the complexity of event signal coordination, token generation, and data readiness signaling, making asynchronous circuits easier to operate while preserving speed advantages.
Data Source
AI summary
A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and converting one or more asynchronous inputs at a circuit boundary to an asynchronous input to the converted asynchronous circuit logic, such that the converted asynchronous input is operable to generate a token upon observing a change in state on the asynchronous input. One or more asynchronous outputs at a circuit boundary is converted to an asynchronous output from the converted asynchronous circuit logic, such that the converted asynchronous output is operable to output updated data as soon as changed data is received from the converted asynchronous circuit logic in the asynchronous output.