Asynchronous Circuit Redundancy for Single-Event Fault Tolerance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Asynchronous electronic circuits are vulnerable to transient faults caused by radiation effects, such as single-event upsets (SEUs), which can lead to deadlocks and incorrect data computation, and existing fault-tolerant solutions are primarily designed for synchronous circuits and not applicable to asynchronous circuits.
Innovation Solution
The design of fault-tolerant asynchronous circuits using replicated logic circuits and staticizer circuits with C-elements to prevent transient faults, ensuring that only one replica is affected by a single-event effect, allowing the other to correct errors and maintain functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If asynchronous circuits are used to eliminate clock signal and filtering, then circuit speed and flexibility are improved, but vulnerability to transient faults and radiation effects increases
Solution Approach 1:
The patent implements fault tolerance by creating duplicate copies of logic circuits and using C-elements to combine their outputs. When a transient fault affects one copy, the other copy produces the correct output, and the C-element selects the valid signal, thereby maintaining reliability without sacrificing asynchronous operation speed.
Solution Approach 2:
The patent prepares for potential radiation effects and transient faults by pre-structuring the circuit with redundant logic paths and C-elements before faults occur. This proactive design ensures that when single-event effects happen, the circuit already has the necessary components in place to filter and correct the faults, maintaining reliability in high-radiation environments.
2Reliability
If replicated logic circuits are used to achieve fault tolerance, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent uses replication of logic circuits combined with C-elements to achieve fault tolerance. By creating duplicate logic paths and using simple C-element combining logic, the system gains reliability against single-event effects while keeping the complexity increase manageable through modular design.
Solution Approach 2:
The patent divides the logic circuit into separable functional units that can be independently replicated. This segmentation allows the fault-tolerant design to be built from modular components, making the complexity more manageable and enabling systematic implementation of redundant logic paths with C-elements.
Data Source
AI summary
New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.