Asynchronous Comparator Bias Control for Low-Power Fast Response
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Solution Overview
Problem
Conventional high-speed comparators face challenges in operating under low voltage conditions with low power consumption and have limitations in controlling bias current accurately, leading to increased propagation delay and large variations in processing.
Innovation Solution
A comparator design with a bias current stage that provides bias current in correspondence with the input signals, utilizing feedback from the comparator's output to control the bias current, eliminating the need for an external current generator and reducing power consumption while decreasing propagation delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If additional circuitry is employed to generate bias signal for high-speed operation, then speed of operation is improved, but area occupied by the comparator increases
Solution Approach 1:
The patent extracts the bias signal generation function from external additional circuitry and implements it within the comparator itself using the existing differential input signals. This eliminates the need for separate bias generation circuitry while maintaining high-speed operation capability.
Solution Approach 2:
The differential input signals serve dual purposes: they perform the primary comparison function and simultaneously generate the bias signal needed for high-speed operation. This multi-functionality reduces the overall circuit area by eliminating dedicated bias generation circuitry.
2Speed
If bias current is increased to reduce propagation delay, then speed of operation is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic bias current adjustment where the bias current automatically adapts based on the differential input signal magnitude. When the differential voltage is small (requiring faster response), the bias current increases to reduce propagation delay. When the differential voltage is large (less critical timing), the bias current decreases to reduce power consumption.
Solution Approach 2:
The comparator uses feedback from the differential input signals to control the bias current generation. The bias current stage monitors the input signal differential and adjusts the bias current accordingly, creating a closed-loop system that optimizes the trade-off between speed and power consumption.
3Device complexity
If conventional bias current generation is used, then circuit simplicity is maintained, but control accuracy over bias current is insufficient
Solution Approach 1:
The comparator circuit serves itself by using its own differential input signals to generate and control the bias current. This self-service approach maintains circuit simplicity while achieving accurate bias current control, as the control mechanism is derived from the circuit's own operating signals rather than requiring external control circuitry.
Data Source
AI summary
The invention relates to an asynchronous comparator that presents low average power consumption and short propagation delay. The comparator bias current is dependent on the differential input voltage in a way that the current increases when the differential input voltage is low and decreases when the differential input voltage is high.