Asynchronous Comparator Clocking for Faster SAR ADC Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In high-speed Successive Approximation Register (SAR) ADCs, comparator delays, particularly the variable metastable delay associated with the regenerative response, limit conversion speed and necessitate worst-case estimation allocation in each SAR loop, leading to inefficiencies.
Innovation Solution
The implementation of an asynchronous clock generation circuit using time-interleaved comparators and a clocking circuit that generates independent asynchronous clock signals, allowing only necessary delays in each SAR cycle and enabling programmable delays to improve DAC setting time over PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If synchronous clock scheme is used to trigger the comparator, then the conversion speed is limited by worst-case comparator delay estimation, but the clocking is simple and synchronized
Solution Approach 1:
The patent transitions from a static synchronous clocking scheme to a dynamic asynchronous clocking scheme where the clock signal is generated based on real-time detection of comparator decision validity. The clock edge is dynamically adjusted to occur immediately after the comparator output becomes valid, eliminating fixed worst-case delay allocation and enabling faster conversion cycles adapted to actual signal conditions.
Solution Approach 2:
The invention implements feedback by monitoring the comparator output validity and using this information to control the clock signal generation. The system detects when the comparator has reached a valid decision state and uses this feedback to trigger the next clock edge, creating a closed-loop system that optimizes timing based on actual comparator performance rather than predetermined worst-case estimates.
2Productivity
If smaller capacitor values are used in CDAC to realize high conversion rates, then the conversion rate increases, but the comparator delay becomes more significant relative to the conversion cycle
Solution Approach 1:
The patent applies dynamic clocking that adapts to the actual comparator decision time, allowing the system to maximize conversion rate with smaller CDAC capacitors. By adjusting the clock timing dynamically based on when the comparator actually becomes valid, the system can tolerate the relatively larger comparator delay that accompanies smaller capacitor values, thereby maintaining high conversion rates that would otherwise be limited by fixed synchronous timing.
3Speed
If asynchronous clock generation is implemented to eliminate worst-case delay allocation, then conversion speed improves, but the clocking circuit complexity increases
Solution Approach 1:
The patent introduces an intermediary validity detection mechanism that monitors comparator output states and mediates between the comparator and clock generation. This intermediary component detects when the comparator reaches a valid decision and uses this information to control clock edges, providing a relatively simple interface that achieves asynchronous timing without requiring complex circuitry throughout the entire system.
Data Source
AI summary
A circuit for asynchronous clock generation is described. The circuit comprises a first comparator configured to receive an analog input signal; a second comparator configured to receive the analog input signal; and a clocking circuit coupled to the first comparator and the second comparator; wherein the clocking circuit generates a first asynchronous clock signal for the first comparator and a second asynchronous clock signal for the second comparator. A method of providing asynchronous clock generation is also described.