Asynchronous Comparator With Dynamic Bias for Low-Voltage Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional high-speed comparators face challenges in operating under low voltage conditions with low power consumption and have limitations in controlling bias current and propagation delay, often requiring external current references and additional circuitry.
Innovation Solution
The comparator incorporates a bias current stage that provides bias current based on input signals with feedback from the comparator output, eliminating the need for external current generators and reducing propagation delay while maintaining low power consumption, featuring a start-up stage and current mirror configuration for stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If additional circuitry is added to generate bias signal for high-speed operation, then speed of operation is improved, but device area increases
Solution Approach 1:
The patent combines the bias generation function with the existing differential input stage by using one of the input transistors to generate the bias current. This merging eliminates the need for separate bias generation circuitry, achieving high-speed operation without increasing device area.
Solution Approach 2:
The input transistor serves multiple functions: it acts as part of the differential input pair for signal comparison and simultaneously generates the bias current for the differential stage. This multi-functionality reduces the overall circuit area while maintaining high-speed performance.
2Speed
If bias current is increased to reduce propagation delay, then speed of operation is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic bias current adjustment where the bias current varies based on the differential input voltage. When the differential voltage is small (near decision threshold), bias current increases to reduce propagation delay. When differential voltage is large, bias current decreases to reduce power consumption.
Solution Approach 2:
The bias current parameter is changed dynamically based on the operating conditions. The circuit automatically adjusts the bias current level according to the differential input voltage, optimizing the trade-off between speed and power consumption for different signal conditions.
3Measurement precision
If external current reference is used for adaptive bias control, then control precision is improved, but device complexity increases
Solution Approach 1:
The comparator circuit generates its own bias current using one of its input transistors, eliminating the need for external current references. This self-service approach maintains precise bias control while reducing device complexity and external component requirements.
Solution Approach 2:
The patent extracts the bias generation function from external components and relocates it within the comparator itself. By taking out the external current reference requirement and implementing internal bias generation, the circuit achieves precise control without the complexity of external references.
Data Source
Figure 1~2
Figure 3
AI summary
The invention relates to an asynchronous comparator that presents low average power consumption and short propagation delay. The comparator bias current is dependent on the differential input voltage in a way that the current increases when the differential input voltage is low and decreases when the differential input voltage is high.