Asynchronous Interconnect Tile Crossbars for Clock-Free Dataflow
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Solution Overview
Problem
Synchronous networks in programmable devices face limitations in pipelining due to clock jitter and skew, making it difficult to achieve functional correctness, while asynchronous networks offer flexibility but require handshaking and fan-out, which have their own disadvantages.
Innovation Solution
Implementing an asynchronous network using interconnect tiles that form pipelines with handshaking protocols, allowing data transfer without relying on a shared clock, and utilizing intermediate primitives to configure programmable logic, which reduces the need for complex clock management and timing constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If synchronous networks are used to transfer data between CLEs, then data transfer frequency is limited to clock speed, but pipelining can increase throughput
Solution Approach 1:
The patent replaces the mechanical clock-based synchronous timing system with an asynchronous event-driven system. Data transfer is triggered by data arrival events rather than clock edges, eliminating the need for clock distribution networks and timing synchronization infrastructure.
Solution Approach 2:
The patent changes the fundamental timing parameter from fixed clock cycles to variable event-driven timing. Each data transfer occurs at the moment data is ready, allowing different parallel paths to operate at different speeds without requiring matched pipeline stages.
2Productivity
If pipelining is implemented in synchronous networks, then throughput increases, but parallel paths must match each other to maintain functional correctness
Solution Approach 1:
The patent introduces dynamic timing where each pipeline stage operates independently based on data readiness. The handshaking protocol allows pipeline stages to proceed at different rates, with downstream stages waiting for upstream stages to produce data rather than all stages advancing in lockstep.
Solution Approach 2:
The patent segments the pipeline into independent stages with explicit handshaking boundaries. Each stage can be configured with different depths and operations, allowing parallel paths to have different lengths and complexities while maintaining functional correctness through independent stage completion signals.
3Adaptability or versatility
If asynchronous networks are used to transfer data, then different parallel paths can have different lengths and perform pipelining, but handshaking and fan-out are required
Solution Approach 1:
The patent implements universal handshaking logic that serves multiple functions: data transfer control, pipeline stage synchronization, and error detection. The same handshaking mechanism is used across all pipeline stages and parallel paths, reducing the need for specialized control circuitry.
4Speed
If synchronous networks are used, then clock distribution is required, but clock jitter and skew limit performance
Solution Approach 1:
The patent replaces the physical clock distribution network with a logical event-driven synchronization system. Instead of propagating a physical clock signal throughout the device, timing is determined by data arrival events and handshaking signals, eliminating jitter and skew inherent in clock distribution.
Data Source
AI summary
An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.