Asynchronous Data Buffer With Inverted Valid Bits
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Solution Overview
Problem
Asynchronous data transfer between systems in different clock domains faces challenges such as increased latency and data corruption due to metastability issues, and existing solutions like two-stage synchronizers and two-phase handshake methods have undesirable trade-offs between performance and reliability, often requiring resetting or clearing of valid bits, which limits efficiency and data throughput.
Innovation Solution
An asynchronous data buffer that uses input and output control logic circuitry to create and invert valid bits for each data burst, allowing simultaneous access and reducing metastability risks without the need for resetting or clearing valid bits, thereby enhancing data throughput and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two-stage synchronizers and two-phase handshake methods are used for asynchronous data transfer, then data synchronization reliability is improved, but system complexity and latency increase
Solution Approach 1:
The patent extracts the valid bit signal from the data elements and handles it separately through dedicated control logic. The valid bit is generated independently by control logic that monitors the data buffer status, allowing data elements to be transferred without complex synchronization logic while maintaining reliability through the separate valid bit management mechanism.
Solution Approach 2:
The patent introduces control logic as an intermediary between the data buffer and the data elements. This control logic generates valid bits based on the data buffer's operational state, acting as a mediator that simplifies the synchronization process. The control logic monitors when data is valid in the buffer and accordingly sets the valid bit, eliminating the need for complex two-stage synchronizers.
2Reliability
If valid bits are reset after each transaction using a data sampler, then data corruption is reduced, but data throughput is limited due to memory location unavailability
Solution Approach 1:
The patent performs preliminary action by pre-positioning the valid bit in the memory location before data transfer begins. The control logic generates the valid bit in advance based on the data buffer's state, and this valid bit is immediately available in the memory location. This eliminates the need to wait for valid bit resetting after each transaction, allowing continuous data throughput without interruption.
Solution Approach 2:
The patent enables continuity of useful action by maintaining the valid bit in the memory location throughout the data transfer process. Instead of resetting the valid bit after each transaction which creates idle time, the valid bit remains continuously available in the memory location, allowing the data buffer to continuously accept and transfer data without interruption, thereby maximizing data throughput.
3Reliability
If synchronous data transfer is used, then data communication reliability is improved, but design flexibility is reduced due to strong clock domain linkage
Solution Approach 1:
The patent segments the data transfer process into two independent parts: data elements and valid bits. The data elements can be transferred asynchronously without requiring clock synchronization, while the valid bits are managed separately by control logic that monitors the data buffer state. This segmentation allows the system to achieve reliability through valid bit management while maintaining design flexibility through asynchronous data transfer.
Data Source
AI summary
The present invention relates to an asynchronous data buffer for transferring m data elements of a burst-transfer between two asynchronous systems. The asynchronous data buffer comprises a data memory for storing m data elements of a data burst and a valid bit memory for storing m input valid bits corresponding to the m data elements. Input control logic circuitry generates the m input valid bits and controls storage of the same and the m data elements. After storage of the m input valid bits an input control signal is provided for inverting the input valid bits of a following data burst. Therefore, after each burst-transfer of m data elements the input valid bit is inverted, automatically rendering all data elements of a previous burst-transfer invalid.