Asynchronous Data Exchange via Status Line
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Solution Overview
Problem
Existing methods for data exchange between main processors and sub-processors require synchronization and are interrupt-dependent, limiting their ability to operate asynchronously and efficiently.
Innovation Solution
A method involving a status line to indicate readiness to receive data, allowing asynchronous data exchange without synchronization, using a serial peripheral interface (SPI) with a separate status line for indicating readiness and additional lines for checking processor availability, ensuring uninterrupted and error-minimized data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If processors are synchronized via system clock for data exchange, then data transmission is reliable, but the system cannot operate asynchronously and loses flexibility
Solution Approach 1:
A status line is introduced as an intermediary signal between master and slave processors to mediate data exchange timing. The status line carries readiness information that allows asynchronous processors to coordinate data transmission without requiring system clock synchronization, thus maintaining reliability while enabling asynchronous operation.
2Productivity
If interrupt-dependent data exchange is used between processors, then data can be transmitted, but deterministic runtime cannot be guaranteed and system stability is reduced
Solution Approach 1:
The slave processor autonomously manages its own data readiness status by setting the status line when ready to receive data and clearing it when data is received. This self-service mechanism eliminates the need for interrupt-dependent coordination, providing deterministic runtime and improved system stability while maintaining productive data exchange.
3Reliability
If transmission data is sent during sub-processor readiness time, then data loss may occur, but if transmission is delayed, the readiness time is wasted
Solution Approach 1:
The master processor prepares transmission data in advance and holds it ready before the slave processor indicates readiness on the status line. When the status line changes state indicating readiness, the master processor immediately transmits the pre-prepared data, ensuring no data loss occurs and the readiness time is fully utilized without waste.
Data Source
AI summary
A method for data exchange between a main processor and at least one sub-processor running asynchronously thereto. The method includes: continuously querying a status line for the data transmission by means of the main processor;preparing transmission data of the sub-processor to the main processor; changing the status of the status line via the sub-processor; starting data transmission from the main processor to the sub-processor, and simultaneously transmitting the transmission data from the sub-processor to the main processor.